/*************************************************************************************
*************************************************************************************
*                                                                                   *
*  Revision      :  $Id: eagle_tsc_fields_public.h 924 2015-02-24 18:08:11Z eroes $ *
*                                                                                   *
*  Description   :  Register access macros for EAGLE_TSC                           *
*                                                                                   *
* Copyright: (c) 2018 Broadcom. All Rights Reserved. "Broadcom" refers to 
* Broadcom Limited and/or its subsidiaries.
* 
* Broadcom Switch Software License
* 
* This license governs the use of the accompanying Broadcom software. Your 
* use of the software indicates your acceptance of the terms and conditions 
* of this license. If you do not agree to the terms and conditions of this 
* license, do not use the software.
* 1. Definitions
*    "Licensor" means any person or entity that distributes its Work.
*    "Software" means the original work of authorship made available under 
*    this license.
*    "Work" means the Software and any additions to or derivative works of 
*    the Software that are made available under this license.
*    The terms "reproduce," "reproduction," "derivative works," and 
*    "distribution" have the meaning as provided under U.S. copyright law.
*    Works, including the Software, are "made available" under this license 
*    by including in or with the Work either (a) a copyright notice 
*    referencing the applicability of this license to the Work, or (b) a copy 
*    of this license.
* 2. Grant of Copyright License
*    Subject to the terms and conditions of this license, each Licensor 
*    grants to you a perpetual, worldwide, non-exclusive, and royalty-free 
*    copyright license to reproduce, prepare derivative works of, publicly 
*    display, publicly perform, sublicense and distribute its Work and any 
*    resulting derivative works in any form.
* 3. Grant of Patent License
*    Subject to the terms and conditions of this license, each Licensor 
*    grants to you a perpetual, worldwide, non-exclusive, and royalty-free 
*    patent license to make, have made, use, offer to sell, sell, import, and 
*    otherwise transfer its Work, in whole or in part. This patent license 
*    applies only to the patent claims licensable by Licensor that would be 
*    infringed by Licensor's Work (or portion thereof) individually and 
*    excluding any combinations with any other materials or technology.
*    If you institute patent litigation against any Licensor (including a 
*    cross-claim or counterclaim in a lawsuit) to enforce any patents that 
*    you allege are infringed by any Work, then your patent license from such 
*    Licensor to the Work shall terminate as of the date such litigation is 
*    filed.
* 4. Redistribution
*    You may reproduce or distribute the Work only if (a) you do so under 
*    this License, (b) you include a complete copy of this License with your 
*    distribution, and (c) you retain without modification any copyright, 
*    patent, trademark, or attribution notices that are present in the Work.
* 5. Derivative Works
*    You may specify that additional or different terms apply to the use, 
*    reproduction, and distribution of your derivative works of the Work 
*    ("Your Terms") only if (a) Your Terms provide that the limitations of 
*    Section 7 apply to your derivative works, and (b) you identify the 
*    specific derivative works that are subject to Your Terms. 
*    Notwithstanding Your Terms, this license (including the redistribution 
*    requirements in Section 4) will continue to apply to the Work itself.
* 6. Trademarks
*    This license does not grant any rights to use any Licensor's or its 
*    affiliates' names, logos, or trademarks, except as necessary to 
*    reproduce the notices described in this license.
* 7. Limitations
*    Platform. The Work and any derivative works thereof may only be used, or 
*    intended for use, with a Broadcom switch integrated circuit.
*    No Reverse Engineering. You will not use the Work to disassemble, 
*    reverse engineer, decompile, or attempt to ascertain the underlying 
*    technology of a Broadcom switch integrated circuit.
* 8. Termination
*    If you violate any term of this license, then your rights under this 
*    license (including the license grants of Sections 2 and 3) will 
*    terminate immediately.
* 9. Disclaimer of Warranty
*    THE WORK IS PROVIDED "AS IS" WITHOUT WARRANTIES OR CONDITIONS OF ANY 
*    KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WARRANTIES OR CONDITIONS OF 
*    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR 
*    NON-INFRINGEMENT. YOU BEAR THE RISK OF UNDERTAKING ANY ACTIVITIES UNDER 
*    THIS LICENSE. SOME STATES' CONSUMER LAWS DO NOT ALLOW EXCLUSION OF AN 
*    IMPLIED WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO YOU.
* 10. Limitation of Liability
*    EXCEPT AS PROHIBITED BY APPLICABLE LAW, IN NO EVENT AND UNDER NO LEGAL 
*    THEORY, WHETHER IN TORT (INCLUDING NEGLIGENCE), CONTRACT, OR OTHERWISE 
*    SHALL ANY LICENSOR BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY DIRECT, 
*    INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF 
*    OR RELATED TO THIS LICENSE, THE USE OR INABILITY TO USE THE WORK 
*    (INCLUDING BUT NOT LIMITED TO LOSS OF GOODWILL, BUSINESS INTERRUPTION, 
*    LOST PROFITS OR DATA, COMPUTER FAILURE OR MALFUNCTION, OR ANY OTHER 
*    COMMERCIAL DAMAGES OR LOSSES), EVEN IF THE LICENSOR HAS BEEN ADVISED OF 
*    THE POSSIBILITY OF SUCH DAMAGES.
* 
*                                                              *
*  No portions of this material may be reproduced in any form without               *
*  the written permission of:                                                       *
*      Broadcom Corporation                                                         *
*      5300 California Avenue                                                       *
*      Irvine, CA  92617                                                            *
*                                                                                   *
*  All information contained in this document is Broadcom Corporation               *
*  company private proprietary, and trade secret.                                   *
 */

/** @file eagle_tsc_fields.h
 * Register access macros for EAGLE_TSC
 */

/* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */

#ifndef EAGLE_TSC_FIELDS_PUBLIC_H
#define EAGLE_TSC_FIELDS_PUBLIC_H

#define rdc_eagle_tsc_ams_pll_cal_aux()                         _eagle_tsc_pmd_rde_field_byte(0xd0b0, 0, 12, __ERR)
#define wrc_eagle_tsc_ams_pll_cal_aux(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0xf000, 12, wr_val)
#define rdc_eagle_tsc_ams_pll_cal_off()                         _eagle_tsc_pmd_rde_field_byte(0xd0b0, 4, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_cal_off(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_iclkidrv1()                 _eagle_tsc_pmd_rde_field_byte(0xd0b0, 5, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_iclkidrv1(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_iclkidrv1()                  _eagle_tsc_pmd_rde_field_byte(0xd0b0, 6, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_iclkidrv1(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0200, 9, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_iclkidrv1()                  _eagle_tsc_pmd_rde_field_byte(0xd0b0, 7, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_iclkidrv1(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0100, 8, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_ickgen()                    _eagle_tsc_pmd_rde_field_byte(0xd0b0, 8, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_ickgen(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_ickgen()                     _eagle_tsc_pmd_rde_field_byte(0xd0b0, 9, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_ickgen(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_ickgen()                     _eagle_tsc_pmd_rde_field_byte(0xd0b0, 10, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_ickgen(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_iclkint()                   _eagle_tsc_pmd_rde_field_byte(0xd0b0, 11, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_iclkint(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_iclkint()                    _eagle_tsc_pmd_rde_field_byte(0xd0b0, 12, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_iclkint(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_iclkint()                    _eagle_tsc_pmd_rde_field_byte(0xd0b0, 13, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_iclkint(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_ams_pll_txcg_vddr_bgb()                   _eagle_tsc_pmd_rde_field_byte(0xd0b0, 14, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_txcg_vddr_bgb(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_ams_pll_lowpwr_6g()                       _eagle_tsc_pmd_rde_field_byte(0xd0b0, 15, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_lowpwr_6g(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b0, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_enable_ftune()                    _eagle_tsc_pmd_rde_field_byte(0xd0b1, 0, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_enable_ftune(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_ams_pll_reset()                           _eagle_tsc_pmd_rde_field_byte(0xd0b1, 1, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_reset(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_ams_pll_ivco()                            _eagle_tsc_pmd_rde_field_byte(0xd0b1, 2, 13, __ERR)
#define wrc_eagle_tsc_ams_pll_ivco(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x3800, 11, wr_val)
#define rdc_eagle_tsc_ams_pll_vco_imax()                        _eagle_tsc_pmd_rde_field_byte(0xd0b1, 5, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_vco_imax(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_ams_pll_vcoictrl()                        _eagle_tsc_pmd_rde_field_byte(0xd0b1, 6, 14, __ERR)
#define wrc_eagle_tsc_ams_pll_vcoictrl(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0300, 8, wr_val)
#define rdc_eagle_tsc_ams_pll_vco_div4()                        _eagle_tsc_pmd_rde_field_byte(0xd0b1, 8, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_vco_div4(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_ams_pll_vco_div2()                        _eagle_tsc_pmd_rde_field_byte(0xd0b1, 9, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_vco_div2(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_ams_pll_fp3_ctrl()                        _eagle_tsc_pmd_rde_field_byte(0xd0b1, 10, 14, __ERR)
#define wrc_eagle_tsc_ams_pll_fp3_ctrl(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0030, 4, wr_val)
#define rdc_eagle_tsc_ams_pll_fp3_rh()                          _eagle_tsc_pmd_rde_field_byte(0xd0b1, 12, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_fp3_rh(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_ams_pll_spare_18()                        _eagle_tsc_pmd_rde_field_byte(0xd0b1, 13, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_spare_18(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_ams_pll_dblr_ctrl()                       _eagle_tsc_pmd_rde_field_byte(0xd0b1, 14, 14, __ERR)
#define wrc_eagle_tsc_ams_pll_dblr_ctrl(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b1, 0x0003, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_ick()                        _eagle_tsc_pmd_rde_field_byte(0xd0b2, 0, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_ick(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_ick()                       _eagle_tsc_pmd_rde_field_byte(0xd0b2, 1, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_ick(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_ick()                        _eagle_tsc_pmd_rde_field_byte(0xd0b2, 2, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_ick(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x2000, 13, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_icp()                        _eagle_tsc_pmd_rde_field_byte(0xd0b2, 3, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_icp(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x1000, 12, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_icp()                       _eagle_tsc_pmd_rde_field_byte(0xd0b2, 4, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_icp(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_icp()                        _eagle_tsc_pmd_rde_field_byte(0xd0b2, 5, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_icp(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_ibias()                      _eagle_tsc_pmd_rde_field_byte(0xd0b2, 6, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_ibias(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0200, 9, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_ibias()                     _eagle_tsc_pmd_rde_field_byte(0xd0b2, 7, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_ibias(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0100, 8, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_ibias()                      _eagle_tsc_pmd_rde_field_byte(0xd0b2, 8, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_ibias(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_ams_pll_refh_pll()                        _eagle_tsc_pmd_rde_field_byte(0xd0b2, 9, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_refh_pll(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_ams_pll_refl_pll()                        _eagle_tsc_pmd_rde_field_byte(0xd0b2, 10, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_refl_pll(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_ams_pll_iqp()                             _eagle_tsc_pmd_rde_field_byte(0xd0b2, 11, 12, __ERR)
#define wrc_eagle_tsc_ams_pll_iqp(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x001e, 1, wr_val)
#define rdc_eagle_tsc_ams_pll_en_hrz()                          _eagle_tsc_pmd_rde_field_byte(0xd0b2, 15, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_en_hrz(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd0b2, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_test_rx()                         _eagle_tsc_pmd_rde_field_byte(0xd0b3, 0, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_test_rx(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_ams_pll_test_pll()                        _eagle_tsc_pmd_rde_field_byte(0xd0b3, 1, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_test_pll(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_ams_pll_test_vc()                         _eagle_tsc_pmd_rde_field_byte(0xd0b3, 2, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_test_vc(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x2000, 13, wr_val)
#define rdc_eagle_tsc_ams_pll_test_vref()                       _eagle_tsc_pmd_rde_field_byte(0xd0b3, 3, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_test_vref(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x1000, 12, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_iop()                        _eagle_tsc_pmd_rde_field_byte(0xd0b3, 4, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_iop(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_iop()                       _eagle_tsc_pmd_rde_field_byte(0xd0b3, 5, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_iop(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_iop()                        _eagle_tsc_pmd_rde_field_byte(0xd0b3, 6, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_iop(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0200, 9, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_icomp()                      _eagle_tsc_pmd_rde_field_byte(0xd0b3, 7, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_icomp(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0100, 8, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_icomp()                     _eagle_tsc_pmd_rde_field_byte(0xd0b3, 8, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_icomp(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_icomp()                      _eagle_tsc_pmd_rde_field_byte(0xd0b3, 9, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_icomp(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_icml()                       _eagle_tsc_pmd_rde_field_byte(0xd0b3, 10, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_icml(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_icml()                      _eagle_tsc_pmd_rde_field_byte(0xd0b3, 11, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_icml(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_icml()                       _eagle_tsc_pmd_rde_field_byte(0xd0b3, 12, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_icml(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_ams_pll_imax_i10gbuf()                    _eagle_tsc_pmd_rde_field_byte(0xd0b3, 13, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imax_i10gbuf(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_ams_pll_imode_i10gbuf()                   _eagle_tsc_pmd_rde_field_byte(0xd0b3, 14, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imode_i10gbuf(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_ams_pll_imin_i10gbuf()                    _eagle_tsc_pmd_rde_field_byte(0xd0b3, 15, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_imin_i10gbuf(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b3, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_force_rescal()                    _eagle_tsc_pmd_rde_field_byte(0xd0b4, 0, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_force_rescal(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_ams_pll_force_kvh_bw()                    _eagle_tsc_pmd_rde_field_byte(0xd0b4, 1, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_force_kvh_bw(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_ams_pll_kvh_force()                       _eagle_tsc_pmd_rde_field_byte(0xd0b4, 2, 14, __ERR)
#define wrc_eagle_tsc_ams_pll_kvh_force(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x3000, 12, wr_val)
#define rdc_eagle_tsc_ams_pll_vddr_bgb()                        _eagle_tsc_pmd_rde_field_byte(0xd0b4, 4, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_vddr_bgb(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_ams_pll_comp_vth()                        _eagle_tsc_pmd_rde_field_byte(0xd0b4, 5, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_comp_vth(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_ams_pll_2rx_clkbw()                       _eagle_tsc_pmd_rde_field_byte(0xd0b4, 6, 14, __ERR)
#define wrc_eagle_tsc_ams_pll_2rx_clkbw(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x0300, 8, wr_val)
#define rdc_eagle_tsc_ams_pll_bgr_ctatadj()                     _eagle_tsc_pmd_rde_field_byte(0xd0b4, 8, 12, __ERR)
#define wrc_eagle_tsc_ams_pll_bgr_ctatadj(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x00f0, 4, wr_val)
#define rdc_eagle_tsc_ams_pll_bgr_ptatadj()                     _eagle_tsc_pmd_rde_field_byte(0xd0b4, 12, 12, __ERR)
#define wrc_eagle_tsc_ams_pll_bgr_ptatadj(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b4, 0x000f, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_bgcalr_ptatadj()                  _eagle_tsc_pmd_rde_field_byte(0xd0b5, 0, 11, __ERR)
#define wrc_eagle_tsc_ams_pll_bgcalr_ptatadj(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0b5, 0xf800, 11, wr_val)
#define rdc_eagle_tsc_ams_pll_bgcalr_ctatadj()                  _eagle_tsc_pmd_rde_field_byte(0xd0b5, 5, 11, __ERR)
#define wrc_eagle_tsc_ams_pll_bgcalr_ctatadj(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0b5, 0x07c0, 6, wr_val)
#define rdc_eagle_tsc_ams_pll_test_pnp()                        _eagle_tsc_pmd_rde_field_byte(0xd0b5, 10, 14, __ERR)
#define wrc_eagle_tsc_ams_pll_test_pnp(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b5, 0x0030, 4, wr_val)
#define rdc_eagle_tsc_ams_pll_vbypass()                         _eagle_tsc_pmd_rde_field_byte(0xd0b5, 12, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_vbypass(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0b5, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_ams_pll_bgint()                           _eagle_tsc_pmd_rde_field_byte(0xd0b5, 13, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_bgint(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0b5, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_ams_pll_bgip()                            _eagle_tsc_pmd_rde_field_byte(0xd0b5, 14, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_bgip(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd0b5, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_ams_pll_max_test_port_ampl()              _eagle_tsc_pmd_rde_field_byte(0xd0b5, 15, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_max_test_port_ampl(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd0b5, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_mix2p1cr_ptatadj()                _eagle_tsc_pmd_rde_field_byte(0xd0b6, 0, 11, __ERR)
#define wrc_eagle_tsc_ams_pll_mix2p1cr_ptatadj(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0xf800, 11, wr_val)
#define rdc_eagle_tsc_ams_pll_mix2p1cr_ctatadj()                _eagle_tsc_pmd_rde_field_byte(0xd0b6, 5, 11, __ERR)
#define wrc_eagle_tsc_ams_pll_mix2p1cr_ctatadj(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0x07c0, 6, wr_val)
#define rdc_eagle_tsc_ams_pll_refclk_doubler()                  _eagle_tsc_pmd_rde_field_byte(0xd0b6, 10, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_refclk_doubler(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_ams_pll_spare_100()                       _eagle_tsc_pmd_rde_field_byte(0xd0b6, 11, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_spare_100(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_ams_pll_pdf_ref_skew()                    _eagle_tsc_pmd_rde_field_byte(0xd0b6, 12, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_pdf_ref_skew(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_ams_pll_pdf_fd_skew()                     _eagle_tsc_pmd_rde_field_byte(0xd0b6, 13, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_pdf_fd_skew(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_ams_pll_pdf_skew_enlarge()                _eagle_tsc_pmd_rde_field_byte(0xd0b6, 14, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_pdf_skew_enlarge(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_ams_pll_test_fracn_en()                   _eagle_tsc_pmd_rde_field_byte(0xd0b6, 15, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_test_fracn_en(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd0b6, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_fracn_div_l()                     _eagle_tsc_pmd_rde_reg(0xd0b7, __ERR)
#define wrc_eagle_tsc_ams_pll_fracn_div_l(wr_val)               eagle_tsc_pmd_wr_reg(0xd0b7, wr_val)
#define rdc_eagle_tsc_ams_pll_fracn_sel()                       _eagle_tsc_pmd_rde_field_byte(0xd0b8, 0, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_fracn_sel(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0b8, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_ams_pll_ditheren()                        _eagle_tsc_pmd_rde_field_byte(0xd0b8, 1, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_ditheren(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0b8, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_ams_pll_fracn_ndiv_int()                  _eagle_tsc_pmd_rde_field(0xd0b8, 2, 6, __ERR)
#define wrc_eagle_tsc_ams_pll_fracn_ndiv_int(wr_val)            eagle_tsc_pmd_mwr_reg(0xd0b8, 0x3ff0, 4, wr_val)
#define rdc_eagle_tsc_ams_pll_fracn_bypass()                    _eagle_tsc_pmd_rde_field_byte(0xd0b8, 12, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_fracn_bypass(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b8, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_ams_pll_fracn_divrange()                  _eagle_tsc_pmd_rde_field_byte(0xd0b8, 13, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_fracn_divrange(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0b8, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_ams_pll_fracn_div_h()                     _eagle_tsc_pmd_rde_field_byte(0xd0b8, 14, 14, __ERR)
#define wrc_eagle_tsc_ams_pll_fracn_div_h(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0b8, 0x0003, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_tx_lowpwr_6g()                    _eagle_tsc_pmd_rde_field_byte(0xd0b9, 15, 15, __ERR)
#define wrc_eagle_tsc_ams_pll_tx_lowpwr_6g(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0b9, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_ams_pll_kvh()                             _eagle_tsc_pmd_rde_field_byte(0xd0ba, 0, 14, __ERR)
#define rdc_eagle_tsc_ams_pll_range()                           _eagle_tsc_pmd_rde_field_byte(0xd0ba, 2, 8, __ERR)
#define rdc_eagle_tsc_ams_pll_low()                             _eagle_tsc_pmd_rde_field_byte(0xd0ba, 10, 15, __ERR)
#define rdc_eagle_tsc_ams_pll_ndiv()                            _eagle_tsc_pmd_rde_field_byte(0xd0ba, 12, 12, __ERR)
#define rd_eagle_tsc_ams_rx_imod_commonmode()                   _eagle_tsc_pmd_rde_field_byte(0xd090, 0, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imod_commonmode(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x8000, 15, wr_val)
#define rd_eagle_tsc_ams_rx_imin_commonmode()                   _eagle_tsc_pmd_rde_field_byte(0xd090, 1, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_commonmode(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x4000, 14, wr_val)
#define rd_eagle_tsc_ams_rx_en_10gmode()                        _eagle_tsc_pmd_rde_field_byte(0xd090, 2, 15, __ERR)
#define wr_eagle_tsc_ams_rx_en_10gmode(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x2000, 13, wr_val)
#define rd_eagle_tsc_ams_rx_dc_couple()                         _eagle_tsc_pmd_rde_field_byte(0xd090, 3, 15, __ERR)
#define wr_eagle_tsc_ams_rx_dc_couple(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x1000, 12, wr_val)
#define rd_eagle_tsc_ams_rx_vga_bw_extension()                  _eagle_tsc_pmd_rde_field_byte(0xd090, 4, 15, __ERR)
#define wr_eagle_tsc_ams_rx_vga_bw_extension(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0800, 11, wr_val)
#define rd_eagle_tsc_ams_rx_sigdet_low_power()                  _eagle_tsc_pmd_rde_field_byte(0xd090, 5, 15, __ERR)
#define wr_eagle_tsc_ams_rx_sigdet_low_power(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0400, 10, wr_val)
#define rd_eagle_tsc_ams_rx_sigdet_bypass()                     _eagle_tsc_pmd_rde_field_byte(0xd090, 6, 15, __ERR)
#define wr_eagle_tsc_ams_rx_sigdet_bypass(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0200, 9, wr_val)
#define rd_eagle_tsc_ams_rx_tport_en()                          _eagle_tsc_pmd_rde_field_byte(0xd090, 7, 15, __ERR)
#define wr_eagle_tsc_ams_rx_tport_en(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0100, 8, wr_val)
#define rd_eagle_tsc_ams_rx_vga_output_idle()                   _eagle_tsc_pmd_rde_field_byte(0xd090, 8, 15, __ERR)
#define wr_eagle_tsc_ams_rx_vga_output_idle(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0080, 7, wr_val)
#define rd_eagle_tsc_ams_rx_sig_pwrdn()                         _eagle_tsc_pmd_rde_field_byte(0xd090, 9, 15, __ERR)
#define wr_eagle_tsc_ams_rx_sig_pwrdn(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0040, 6, wr_val)
#define rd_eagle_tsc_ams_rx_sigdet_threshold()                  _eagle_tsc_pmd_rde_field_byte(0xd090, 10, 13, __ERR)
#define wr_eagle_tsc_ams_rx_sigdet_threshold(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0038, 3, wr_val)
#define rd_eagle_tsc_ams_rx_phase_int_ampl_ctrl()               _eagle_tsc_pmd_rde_field_byte(0xd090, 13, 15, __ERR)
#define wr_eagle_tsc_ams_rx_phase_int_ampl_ctrl(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ams_rx_sel_dfeckdelay()                    _eagle_tsc_pmd_rde_field_byte(0xd090, 14, 14, __ERR)
#define wr_eagle_tsc_ams_rx_sel_dfeckdelay(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd090, 0x0003, 0, wr_val)
#define rd_eagle_tsc_ams_rx_imax_ctat()                         _eagle_tsc_pmd_rde_field_byte(0xd091, 0, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_ctat(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x8000, 15, wr_val)
#define rd_eagle_tsc_ams_rx_imode_ctat()                        _eagle_tsc_pmd_rde_field_byte(0xd091, 1, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_ctat(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x4000, 14, wr_val)
#define rd_eagle_tsc_ams_rx_imin_ctat()                         _eagle_tsc_pmd_rde_field_byte(0xd091, 2, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_ctat(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x2000, 13, wr_val)
#define rd_eagle_tsc_ams_rx_imax_pf()                           _eagle_tsc_pmd_rde_field_byte(0xd091, 3, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_pf(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x1000, 12, wr_val)
#define rd_eagle_tsc_ams_rx_imode_pf()                          _eagle_tsc_pmd_rde_field_byte(0xd091, 4, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_pf(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0800, 11, wr_val)
#define rd_eagle_tsc_ams_rx_imin_pf()                           _eagle_tsc_pmd_rde_field_byte(0xd091, 5, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_pf(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0400, 10, wr_val)
#define rd_eagle_tsc_ams_rx_imax_dfe_summer()                   _eagle_tsc_pmd_rde_field_byte(0xd091, 6, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_dfe_summer(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0200, 9, wr_val)
#define rd_eagle_tsc_ams_rx_imode_dfe_summer()                  _eagle_tsc_pmd_rde_field_byte(0xd091, 7, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_dfe_summer(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0100, 8, wr_val)
#define rd_eagle_tsc_ams_rx_imin_dfe_summer()                   _eagle_tsc_pmd_rde_field_byte(0xd091, 8, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_dfe_summer(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0080, 7, wr_val)
#define rd_eagle_tsc_ams_rx_imax_vga()                          _eagle_tsc_pmd_rde_field_byte(0xd091, 9, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_vga(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0040, 6, wr_val)
#define rd_eagle_tsc_ams_rx_imode_vga()                         _eagle_tsc_pmd_rde_field_byte(0xd091, 10, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_vga(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0020, 5, wr_val)
#define rd_eagle_tsc_ams_rx_imin_vga()                          _eagle_tsc_pmd_rde_field_byte(0xd091, 11, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_vga(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0010, 4, wr_val)
#define rd_eagle_tsc_ams_rx_imax_phase_int()                    _eagle_tsc_pmd_rde_field_byte(0xd091, 12, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_phase_int(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0008, 3, wr_val)
#define rd_eagle_tsc_ams_rx_imode_phase_int()                   _eagle_tsc_pmd_rde_field_byte(0xd091, 13, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_phase_int(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ams_rx_imin_phase_int()                    _eagle_tsc_pmd_rde_field_byte(0xd091, 14, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_phase_int(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ams_rx_imax_commonmode()                   _eagle_tsc_pmd_rde_field_byte(0xd091, 15, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_commonmode(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd091, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ams_rx_spare_47()                          _eagle_tsc_pmd_rde_field_byte(0xd092, 0, 15, __ERR)
#define wr_eagle_tsc_ams_rx_spare_47(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x8000, 15, wr_val)
#define rd_eagle_tsc_ams_rx_spare_46()                          _eagle_tsc_pmd_rde_field_byte(0xd092, 1, 15, __ERR)
#define wr_eagle_tsc_ams_rx_spare_46(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x4000, 14, wr_val)
#define rd_eagle_tsc_ams_rx_en_vcctrl()                         _eagle_tsc_pmd_rde_field_byte(0xd092, 2, 15, __ERR)
#define wr_eagle_tsc_ams_rx_en_vcctrl(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x2000, 13, wr_val)
#define rd_eagle_tsc_ams_rx_sel_th4dfe()                        _eagle_tsc_pmd_rde_field_byte(0xd092, 3, 14, __ERR)
#define wr_eagle_tsc_ams_rx_sel_th4dfe(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x1800, 11, wr_val)
#define rd_eagle_tsc_ams_rx_sel_ugbw()                          _eagle_tsc_pmd_rde_field_byte(0xd092, 5, 14, __ERR)
#define wr_eagle_tsc_ams_rx_sel_ugbw(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0600, 9, wr_val)
#define rd_eagle_tsc_ams_rx_imax_dfe_tap_weight()               _eagle_tsc_pmd_rde_field_byte(0xd092, 7, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_dfe_tap_weight(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0100, 8, wr_val)
#define rd_eagle_tsc_ams_rx_imode_dfe_tap_weight()              _eagle_tsc_pmd_rde_field_byte(0xd092, 8, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_dfe_tap_weight(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0080, 7, wr_val)
#define rd_eagle_tsc_ams_rx_imin_dfe_tap_weight()               _eagle_tsc_pmd_rde_field_byte(0xd092, 9, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_dfe_tap_weight(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0040, 6, wr_val)
#define rd_eagle_tsc_ams_rx_imax_slicer()                       _eagle_tsc_pmd_rde_field_byte(0xd092, 10, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_slicer(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0020, 5, wr_val)
#define rd_eagle_tsc_ams_rx_imode_slicer()                      _eagle_tsc_pmd_rde_field_byte(0xd092, 11, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_slicer(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0010, 4, wr_val)
#define rd_eagle_tsc_ams_rx_imin_slicer()                       _eagle_tsc_pmd_rde_field_byte(0xd092, 12, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_slicer(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0008, 3, wr_val)
#define rd_eagle_tsc_ams_rx_spare_34()                          _eagle_tsc_pmd_rde_field_byte(0xd092, 13, 15, __ERR)
#define wr_eagle_tsc_ams_rx_spare_34(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ams_rx_spare_33()                          _eagle_tsc_pmd_rde_field_byte(0xd092, 14, 15, __ERR)
#define wr_eagle_tsc_ams_rx_spare_33(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ams_rx_spare_32()                          _eagle_tsc_pmd_rde_field_byte(0xd092, 15, 15, __ERR)
#define wr_eagle_tsc_ams_rx_spare_32(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd092, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ams_rx_spare_63()                          _eagle_tsc_pmd_rde_field_byte(0xd093, 0, 15, __ERR)
#define wr_eagle_tsc_ams_rx_spare_63(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x8000, 15, wr_val)
#define rd_eagle_tsc_ams_rx_spare_62()                          _eagle_tsc_pmd_rde_field_byte(0xd093, 1, 15, __ERR)
#define wr_eagle_tsc_ams_rx_spare_62(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x4000, 14, wr_val)
#define rd_eagle_tsc_ams_rx_i1p25dfe()                          _eagle_tsc_pmd_rde_field_byte(0xd093, 2, 15, __ERR)
#define wr_eagle_tsc_ams_rx_i1p25dfe(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x2000, 13, wr_val)
#define rd_eagle_tsc_ams_rx_i4deadzone()                        _eagle_tsc_pmd_rde_field_byte(0xd093, 3, 15, __ERR)
#define wr_eagle_tsc_ams_rx_i4deadzone(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x1000, 12, wr_val)
#define rd_eagle_tsc_ams_rx_imax_signal_detect()                _eagle_tsc_pmd_rde_field_byte(0xd093, 4, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_signal_detect(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0800, 11, wr_val)
#define rd_eagle_tsc_ams_rx_imode_signal_detect()               _eagle_tsc_pmd_rde_field_byte(0xd093, 5, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_signal_detect(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0400, 10, wr_val)
#define rd_eagle_tsc_ams_rx_imin_signal_detect()                _eagle_tsc_pmd_rde_field_byte(0xd093, 6, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_signal_detect(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0200, 9, wr_val)
#define rd_eagle_tsc_ams_rx_imax_metres_eyediag()               _eagle_tsc_pmd_rde_field_byte(0xd093, 7, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_metres_eyediag(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0100, 8, wr_val)
#define rd_eagle_tsc_ams_rx_imode_metres_eyediag()              _eagle_tsc_pmd_rde_field_byte(0xd093, 8, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_metres_eyediag(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0080, 7, wr_val)
#define rd_eagle_tsc_ams_rx_imin_metres_eyediag()               _eagle_tsc_pmd_rde_field_byte(0xd093, 9, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_metres_eyediag(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0040, 6, wr_val)
#define rd_eagle_tsc_ams_rx_imax_phase_int_p1()                 _eagle_tsc_pmd_rde_field_byte(0xd093, 10, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_phase_int_p1(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0020, 5, wr_val)
#define rd_eagle_tsc_ams_rx_imode_phase_int_p1()                _eagle_tsc_pmd_rde_field_byte(0xd093, 11, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_phase_int_p1(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0010, 4, wr_val)
#define rd_eagle_tsc_ams_rx_imin_phase_int_p1()                 _eagle_tsc_pmd_rde_field_byte(0xd093, 12, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_phase_int_p1(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0008, 3, wr_val)
#define rd_eagle_tsc_ams_rx_imax_dc_offset_dac()                _eagle_tsc_pmd_rde_field_byte(0xd093, 13, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imax_dc_offset_dac(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ams_rx_imode_dc_offset_dac()               _eagle_tsc_pmd_rde_field_byte(0xd093, 14, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imode_dc_offset_dac(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ams_rx_imin_dc_offset_dac()                _eagle_tsc_pmd_rde_field_byte(0xd093, 15, 15, __ERR)
#define wr_eagle_tsc_ams_rx_imin_dc_offset_dac(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd093, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ams_rx_phs_interp_rescal_mux()             _eagle_tsc_pmd_rde_field_byte(0xd094, 0, 12, __ERR)
#define wr_eagle_tsc_ams_rx_phs_interp_rescal_mux(wr_val)       _eagle_tsc_pmd_mwr_reg_byte(0xd094, 0xf000, 12, wr_val)
#define rd_eagle_tsc_ams_rx_vga_rescal_mux()                    _eagle_tsc_pmd_rde_field_byte(0xd094, 4, 13, __ERR)
#define wr_eagle_tsc_ams_rx_vga_rescal_mux(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd094, 0x0e00, 9, wr_val)
#define rd_eagle_tsc_ams_rx_dc_offset_range()                   _eagle_tsc_pmd_rde_field_byte(0xd094, 7, 15, __ERR)
#define wr_eagle_tsc_ams_rx_dc_offset_range(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd094, 0x0100, 8, wr_val)
#define rd_eagle_tsc_ams_rx_force_dc_offset()                   _eagle_tsc_pmd_rde_field_byte(0xd094, 8, 15, __ERR)
#define wr_eagle_tsc_ams_rx_force_dc_offset(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd094, 0x0080, 7, wr_val)
#define rd_eagle_tsc_ams_rx_dc_offset()                         _eagle_tsc_pmd_rde_field_byte(0xd094, 9, 9, __ERR)
#define wr_eagle_tsc_ams_rx_dc_offset(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd094, 0x007f, 0, wr_val)
#define rd_eagle_tsc_ams_rx_dfe_os2x_mode()                     _eagle_tsc_pmd_rde_field_byte(0xd098, 15, 15, __ERR)
#define wr_eagle_tsc_ams_rx_dfe_os2x_mode(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd098, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ams_rx_sigdet()                            _eagle_tsc_pmd_rde_field_byte(0xd099, 0, 15, __ERR)
#define rd_eagle_tsc_ams_rx_pf()                                _eagle_tsc_pmd_rde_field_byte(0xd099, 1, 12, __ERR)
#define rd_eagle_tsc_ams_rx_tap1_dfe_gray()                     _eagle_tsc_pmd_rde_field_byte(0xd099, 5, 10, __ERR)
#define rd_eagle_tsc_ams_rx_vga()                               _eagle_tsc_pmd_rde_field_byte(0xd099, 11, 11, __ERR)
#define rd_eagle_tsc_ams_tx_cal_aux()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 0, 12, __ERR)
#define wr_eagle_tsc_ams_tx_cal_aux(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0xf000, 12, wr_val)
#define rd_eagle_tsc_ams_tx_cal_off()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 4, 15, __ERR)
#define wr_eagle_tsc_ams_tx_cal_off(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0800, 11, wr_val)
#define rd_eagle_tsc_ams_tx_dcc_dis()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 5, 15, __ERR)
#define wr_eagle_tsc_ams_tx_dcc_dis(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0400, 10, wr_val)
#define rd_eagle_tsc_ams_tx_dcc_sel()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 6, 15, __ERR)
#define wr_eagle_tsc_ams_tx_dcc_sel(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0200, 9, wr_val)
#define rd_eagle_tsc_ams_tx_kr_test_mode()                      _eagle_tsc_pmd_rde_field_byte(0xd0a0, 7, 15, __ERR)
#define wr_eagle_tsc_ams_tx_kr_test_mode(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0100, 8, wr_val)
#define rd_eagle_tsc_ams_tx_ticksel()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 8, 14, __ERR)
#define wr_eagle_tsc_ams_tx_ticksel(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x00c0, 6, wr_val)
#define rd_eagle_tsc_ams_tx_test_data()                         _eagle_tsc_pmd_rde_field_byte(0xd0a0, 10, 14, __ERR)
#define wr_eagle_tsc_ams_tx_test_data(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0030, 4, wr_val)
#define rd_eagle_tsc_ams_tx_spare_3()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 12, 15, __ERR)
#define wr_eagle_tsc_ams_tx_spare_3(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0008, 3, wr_val)
#define rd_eagle_tsc_ams_tx_spare_2()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 13, 15, __ERR)
#define wr_eagle_tsc_ams_tx_spare_2(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ams_tx_spare_1()                           _eagle_tsc_pmd_rde_field_byte(0xd0a0, 14, 15, __ERR)
#define wr_eagle_tsc_ams_tx_spare_1(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ams_tx_osr4()                              _eagle_tsc_pmd_rde_field_byte(0xd0a0, 15, 15, __ERR)
#define wr_eagle_tsc_ams_tx_osr4(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0a0, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ams_tx_lp_ovrd()                           _eagle_tsc_pmd_rde_field_byte(0xd0a1, 0, 15, __ERR)
#define wr_eagle_tsc_ams_tx_lp_ovrd(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a1, 0x8000, 15, wr_val)
#define rd_eagle_tsc_ams_tx_spare_30_25()                       _eagle_tsc_pmd_rde_field_byte(0xd0a1, 1, 10, __ERR)
#define wr_eagle_tsc_ams_tx_spare_30_25(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0a1, 0x7e00, 9, wr_val)
#define rd_eagle_tsc_ams_tx_icml()                              _eagle_tsc_pmd_rde_field_byte(0xd0a1, 7, 13, __ERR)
#define wr_eagle_tsc_ams_tx_icml(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0a1, 0x01c0, 6, wr_val)
#define rd_eagle_tsc_ams_tx_idcc()                              _eagle_tsc_pmd_rde_field_byte(0xd0a1, 10, 13, __ERR)
#define wr_eagle_tsc_ams_tx_idcc(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0a1, 0x0038, 3, wr_val)
#define rd_eagle_tsc_ams_tx_ibias()                             _eagle_tsc_pmd_rde_field_byte(0xd0a1, 13, 13, __ERR)
#define wr_eagle_tsc_ams_tx_ibias(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0a1, 0x0007, 0, wr_val)
#define rd_eagle_tsc_ams_tx_elec_idle_aux()                     _eagle_tsc_pmd_rde_field_byte(0xd0a2, 0, 15, __ERR)
#define wr_eagle_tsc_ams_tx_elec_idle_aux(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0a2, 0x8000, 15, wr_val)
#define rd_eagle_tsc_ams_tx_drivermode()                        _eagle_tsc_pmd_rde_field_byte(0xd0a2, 1, 14, __ERR)
#define wr_eagle_tsc_ams_tx_drivermode(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0a2, 0x6000, 13, wr_val)
#define rd_eagle_tsc_ams_tx_sign_post2()                        _eagle_tsc_pmd_rde_field_byte(0xd0a2, 3, 15, __ERR)
#define wr_eagle_tsc_ams_tx_sign_post2(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0a2, 0x1000, 12, wr_val)
#define rd_eagle_tsc_ams_tx_post2_coef()                        _eagle_tsc_pmd_rde_field_byte(0xd0a2, 4, 12, __ERR)
#define wr_eagle_tsc_ams_tx_post2_coef(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0a2, 0x0f00, 8, wr_val)
#define rd_eagle_tsc_ams_tx_sign_post3()                        _eagle_tsc_pmd_rde_field_byte(0xd0a2, 8, 15, __ERR)
#define wr_eagle_tsc_ams_tx_sign_post3(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0a2, 0x0080, 7, wr_val)
#define rd_eagle_tsc_ams_tx_post3_coef()                        _eagle_tsc_pmd_rde_field_byte(0xd0a2, 9, 13, __ERR)
#define wr_eagle_tsc_ams_tx_post3_coef(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0a2, 0x0070, 4, wr_val)
#define rd_eagle_tsc_ams_tx_amp_ctl()                           _eagle_tsc_pmd_rde_field_byte(0xd0a2, 12, 12, __ERR)
#define wr_eagle_tsc_ams_tx_amp_ctl(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0a2, 0x000f, 0, wr_val)
#define rd_eagle_tsc_ams_tx_sel_halfrate()                      _eagle_tsc_pmd_rde_field_byte(0xd0a8, 15, 15, __ERR)
#define wr_eagle_tsc_ams_tx_sel_halfrate(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0a8, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ams_tx_id()                                _eagle_tsc_pmd_rde_field_byte(0xd0a9, 0, 14, __ERR)
#define rd_eagle_tsc_ams_tx_ana_rescal()                        _eagle_tsc_pmd_rde_field_byte(0xd0a9, 4, 12, __ERR)
#define rd_eagle_tsc_ams_tx_version_id()                        _eagle_tsc_pmd_rde_field_byte(0xd0a9, 8, 8, __ERR)
#define rd_eagle_tsc_osr_mode_frc()                             _eagle_tsc_pmd_rde_field_byte(0xd080, 0, 15, __ERR)
#define wr_eagle_tsc_osr_mode_frc(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd080, 0x8000, 15, wr_val)
#define rd_eagle_tsc_osr_mode_frc_val()                         _eagle_tsc_pmd_rde_field_byte(0xd080, 12, 12, __ERR)
#define wr_eagle_tsc_osr_mode_frc_val(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd080, 0x000f, 0, wr_val)
#define rd_eagle_tsc_afe_sigdet_pwrdn()                         _eagle_tsc_pmd_rde_field_byte(0xd081, 11, 15, __ERR)
#define wr_eagle_tsc_afe_sigdet_pwrdn(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd081, 0x0010, 4, wr_val)
#define rd_eagle_tsc_ln_tx_s_pwrdn()                            _eagle_tsc_pmd_rde_field_byte(0xd081, 12, 15, __ERR)
#define wr_eagle_tsc_ln_tx_s_pwrdn(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd081, 0x0008, 3, wr_val)
#define rd_eagle_tsc_ln_rx_s_pwrdn()                            _eagle_tsc_pmd_rde_field_byte(0xd081, 13, 15, __ERR)
#define wr_eagle_tsc_ln_rx_s_pwrdn(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd081, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ln_dp_s_rstb()                             _eagle_tsc_pmd_rde_field_byte(0xd081, 14, 15, __ERR)
#define wr_eagle_tsc_ln_dp_s_rstb(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd081, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ln_s_rstb()                                _eagle_tsc_pmd_rde_field_byte(0xd08e, 15, 15, __ERR)
#define wr_eagle_tsc_ln_s_rstb(wr_val)                          _eagle_tsc_pmd_mwr_reg_byte(0xd08e, 0x0001, 0, wr_val)
#define rd_eagle_tsc_pmd_rx_clk_vld_frc_val()                   _eagle_tsc_pmd_rde_field_byte(0xd087, 11, 15, __ERR)
#define wr_eagle_tsc_pmd_rx_clk_vld_frc_val(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd087, 0x0010, 4, wr_val)
#define rd_eagle_tsc_pmd_rx_clk_vld_frc()                       _eagle_tsc_pmd_rde_field_byte(0xd087, 12, 15, __ERR)
#define wr_eagle_tsc_pmd_rx_clk_vld_frc(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd087, 0x0008, 3, wr_val)
#define rd_eagle_tsc_ln_rx_s_comclk_frc_on()                    _eagle_tsc_pmd_rde_field_byte(0xd087, 13, 15, __ERR)
#define wr_eagle_tsc_ln_rx_s_comclk_frc_on(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd087, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ln_rx_s_comclk_sel()                       _eagle_tsc_pmd_rde_field_byte(0xd087, 14, 15, __ERR)
#define wr_eagle_tsc_ln_rx_s_comclk_sel(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd087, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ln_rx_s_clkgate_frc_on()                   _eagle_tsc_pmd_rde_field_byte(0xd087, 15, 15, __ERR)
#define wr_eagle_tsc_ln_rx_s_clkgate_frc_on(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd087, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ln_tx_dp_s_rstb()                          _eagle_tsc_pmd_rde_field_byte(0xd084, 6, 15, __ERR)
#define wr_eagle_tsc_ln_tx_dp_s_rstb(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd084, 0x0200, 9, wr_val)
#define rd_eagle_tsc_ln_tx_s_rstb()                             _eagle_tsc_pmd_rde_field_byte(0xd084, 7, 15, __ERR)
#define wr_eagle_tsc_ln_tx_s_rstb(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd084, 0x0100, 8, wr_val)
#define rd_eagle_tsc_sigdet_dp_rstb_en()                        _eagle_tsc_pmd_rde_field_byte(0xd084, 13, 15, __ERR)
#define wr_eagle_tsc_sigdet_dp_rstb_en(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd084, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ln_rx_dp_s_rstb()                          _eagle_tsc_pmd_rde_field_byte(0xd084, 14, 15, __ERR)
#define wr_eagle_tsc_ln_rx_dp_s_rstb(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd084, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ln_rx_s_rstb()                             _eagle_tsc_pmd_rde_field_byte(0xd084, 15, 15, __ERR)
#define wr_eagle_tsc_ln_rx_s_rstb(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd084, 0x0001, 0, wr_val)
#define rd_eagle_tsc_afe_tx_reset_frc_val()                     _eagle_tsc_pmd_rde_field_byte(0xd082, 8, 15, __ERR)
#define wr_eagle_tsc_afe_tx_reset_frc_val(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0080, 7, wr_val)
#define rd_eagle_tsc_afe_tx_reset_frc()                         _eagle_tsc_pmd_rde_field_byte(0xd082, 9, 15, __ERR)
#define wr_eagle_tsc_afe_tx_reset_frc(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0040, 6, wr_val)
#define rd_eagle_tsc_afe_tx_pwrdn_frc_val()                     _eagle_tsc_pmd_rde_field_byte(0xd082, 10, 15, __ERR)
#define wr_eagle_tsc_afe_tx_pwrdn_frc_val(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0020, 5, wr_val)
#define rd_eagle_tsc_afe_tx_pwrdn_frc()                         _eagle_tsc_pmd_rde_field_byte(0xd082, 11, 15, __ERR)
#define wr_eagle_tsc_afe_tx_pwrdn_frc(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0010, 4, wr_val)
#define rd_eagle_tsc_afe_rx_reset_frc_val()                     _eagle_tsc_pmd_rde_field_byte(0xd082, 12, 15, __ERR)
#define wr_eagle_tsc_afe_rx_reset_frc_val(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0008, 3, wr_val)
#define rd_eagle_tsc_afe_rx_reset_frc()                         _eagle_tsc_pmd_rde_field_byte(0xd082, 13, 15, __ERR)
#define wr_eagle_tsc_afe_rx_reset_frc(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0004, 2, wr_val)
#define rd_eagle_tsc_afe_rx_pwrdn_frc_val()                     _eagle_tsc_pmd_rde_field_byte(0xd082, 14, 15, __ERR)
#define wr_eagle_tsc_afe_rx_pwrdn_frc_val(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0002, 1, wr_val)
#define rd_eagle_tsc_afe_rx_pwrdn_frc()                         _eagle_tsc_pmd_rde_field_byte(0xd082, 15, 15, __ERR)
#define wr_eagle_tsc_afe_rx_pwrdn_frc(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd082, 0x0001, 0, wr_val)
#define rd_eagle_tsc_pmd_ln_tx_h_pwrdn_pkill()                  _eagle_tsc_pmd_rde_field_byte(0xd083, 12, 15, __ERR)
#define wr_eagle_tsc_pmd_ln_tx_h_pwrdn_pkill(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd083, 0x0008, 3, wr_val)
#define rd_eagle_tsc_pmd_ln_rx_h_pwrdn_pkill()                  _eagle_tsc_pmd_rde_field_byte(0xd083, 13, 15, __ERR)
#define wr_eagle_tsc_pmd_ln_rx_h_pwrdn_pkill(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd083, 0x0004, 2, wr_val)
#define rd_eagle_tsc_pmd_ln_dp_h_rstb_pkill()                   _eagle_tsc_pmd_rde_field_byte(0xd083, 14, 15, __ERR)
#define wr_eagle_tsc_pmd_ln_dp_h_rstb_pkill(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd083, 0x0002, 1, wr_val)
#define rd_eagle_tsc_pmd_ln_h_rstb_pkill()                      _eagle_tsc_pmd_rde_field_byte(0xd083, 15, 15, __ERR)
#define wr_eagle_tsc_pmd_ln_h_rstb_pkill(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd083, 0x0001, 0, wr_val)
#define rd_eagle_tsc_pmd_lane_mode()                            _eagle_tsc_pmd_rde_reg(0xd088, __ERR)
#define rd_eagle_tsc_uc_ack_lane_dp_reset()                     _eagle_tsc_pmd_rde_field_byte(0xd085, 14, 15, __ERR)
#define wr_eagle_tsc_uc_ack_lane_dp_reset(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd085, 0x0002, 1, wr_val)
#define rd_eagle_tsc_uc_ack_lane_cfg_done()                     _eagle_tsc_pmd_rde_field_byte(0xd085, 15, 15, __ERR)
#define wr_eagle_tsc_uc_ack_lane_cfg_done(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd085, 0x0001, 0, wr_val)
#define rd_eagle_tsc_lane_dp_reset_state()                      _eagle_tsc_pmd_rde_field_byte(0xd089, 13, 13, __ERR)
#define rd_eagle_tsc_lane_reg_reset_occurred()                  _eagle_tsc_pmd_rde_field_byte(0xd086, 15, 15, __ERR)
#define wr_eagle_tsc_lane_reg_reset_occurred(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd086, 0x0001, 0, wr_val)
#define rd_eagle_tsc_lane_multicast_mask_control()              _eagle_tsc_pmd_rde_field_byte(0xd08a, 15, 15, __ERR)
#define wr_eagle_tsc_lane_multicast_mask_control(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd08a, 0x0001, 0, wr_val)
#define rd_eagle_tsc_osr_mode()                                 _eagle_tsc_pmd_rde_field_byte(0xd08b, 12, 12, __ERR)
#define rd_eagle_tsc_osr_mode_pin()                             _eagle_tsc_pmd_rde_field_byte(0xd08c, 12, 12, __ERR)
#define rd_eagle_tsc_cl72_ieee_lp_status_report()               _eagle_tsc_pmd_rde_reg(0x0099, __ERR)
#define rd_eagle_tsc_cl72_ieee_training_enable()                _eagle_tsc_pmd_rde_field_byte(0x0096, 14, 15, __ERR)
#define wr_eagle_tsc_cl72_ieee_training_enable(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0x0096, 0x0002, 1, wr_val)
#define rd_eagle_tsc_cl72_ieee_restart_training()               _eagle_tsc_pmd_rde_field_byte(0x0096, 15, 15, __ERR)
#define wr_eagle_tsc_cl72_ieee_restart_training(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0x0096, 0x0001, 0, wr_val)
#define rd_eagle_tsc_cl72_ieee_training_failure()               _eagle_tsc_pmd_rde_field_byte(0x0097, 12, 15, __ERR)
#define rd_eagle_tsc_cl72_ieee_training_status()                _eagle_tsc_pmd_rde_field_byte(0x0097, 13, 15, __ERR)
#define rd_eagle_tsc_cl72_ieee_frame_lock()                     _eagle_tsc_pmd_rde_field_byte(0x0097, 14, 15, __ERR)
#define rd_eagle_tsc_cl72_ieee_receiver_status()                _eagle_tsc_pmd_rde_field_byte(0x0097, 15, 15, __ERR)
#define rd_eagle_tsc_cl72_ieee_lp_coeff_update()                _eagle_tsc_pmd_rde_reg(0x0098, __ERR)
#define rd_eagle_tsc_cl72_ieee_ld_coeff_update()                _eagle_tsc_pmd_rde_reg(0x009a, __ERR)
#define rd_eagle_tsc_cl72_ieee_ld_status_report()               _eagle_tsc_pmd_rde_reg(0x009b, __ERR)
#define rd_eagle_tsc_cl72_rcvd_status_page()                    _eagle_tsc_pmd_rde_reg(0xd050, __ERR)
#define rd_eagle_tsc_cl72_rx_dp_ln_clk_en()                     _eagle_tsc_pmd_rde_field_byte(0xd051, 13, 15, __ERR)
#define wr_eagle_tsc_cl72_rx_dp_ln_clk_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd051, 0x0004, 2, wr_val)
#define rd_eagle_tsc_cl72_tr_coarse_lock()                      _eagle_tsc_pmd_rde_field_byte(0xd051, 14, 15, __ERR)
#define wr_eagle_tsc_cl72_tr_coarse_lock(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd051, 0x0002, 1, wr_val)
#define rd_eagle_tsc_cl72_ppm_offset_en()                       _eagle_tsc_pmd_rde_field_byte(0xd052, 1, 15, __ERR)
#define wr_eagle_tsc_cl72_ppm_offset_en(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd052, 0x4000, 14, wr_val)
#define rd_eagle_tsc_cl72_strict_marker_chk()                   _eagle_tsc_pmd_rde_field_byte(0xd052, 2, 15, __ERR)
#define wr_eagle_tsc_cl72_strict_marker_chk(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd052, 0x2000, 13, wr_val)
#define rd_eagle_tsc_cl72_strict_dme_chk()                      _eagle_tsc_pmd_rde_field_byte(0xd052, 3, 15, __ERR)
#define wr_eagle_tsc_cl72_strict_dme_chk(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd052, 0x1000, 12, wr_val)
#define rd_eagle_tsc_cl72_ctrl_frame_dly()                      _eagle_tsc_pmd_rde_field_byte(0xd052, 4, 12, __ERR)
#define wr_eagle_tsc_cl72_ctrl_frame_dly(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd052, 0x0f00, 8, wr_val)
#define rd_eagle_tsc_cl72_dme_cell_boundary_chk()               _eagle_tsc_pmd_rde_field_byte(0xd052, 8, 15, __ERR)
#define wr_eagle_tsc_cl72_dme_cell_boundary_chk(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd052, 0x0080, 7, wr_val)
#define rd_eagle_tsc_cl72_bad_marker_cnt()                      _eagle_tsc_pmd_rde_field_byte(0xd052, 11, 13, __ERR)
#define wr_eagle_tsc_cl72_bad_marker_cnt(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd052, 0x001c, 2, wr_val)
#define rd_eagle_tsc_cl72_good_marker_cnt()                     _eagle_tsc_pmd_rde_field_byte(0xd052, 14, 14, __ERR)
#define wr_eagle_tsc_cl72_good_marker_cnt(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd052, 0x0003, 0, wr_val)
#define rd_eagle_tsc_cl72_lp_control_page()                     _eagle_tsc_pmd_rde_reg(0xd053, __ERR)
#define rd_eagle_tsc_cl72_signal_detect()                       _eagle_tsc_pmd_rde_field_byte(0xd054, 15, 15, __ERR)
#define rd_eagle_tsc_cl72_xmt_update_page()                     _eagle_tsc_pmd_rde_reg(0xd060, __ERR)
#define wr_eagle_tsc_cl72_xmt_update_page(wr_val)               eagle_tsc_pmd_wr_reg(0xd060, wr_val)
#define rd_eagle_tsc_cl72_double_cmd_en()                       _eagle_tsc_pmd_rde_field_byte(0xd068, 3, 15, __ERR)
#define wr_eagle_tsc_cl72_double_cmd_en(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd068, 0x1000, 12, wr_val)
#define rd_eagle_tsc_cl72_dis_lp_coeff_updates_to_ld()          _eagle_tsc_pmd_rde_field_byte(0xd068, 4, 15, __ERR)
#define wr_eagle_tsc_cl72_dis_lp_coeff_updates_to_ld(wr_val)    _eagle_tsc_pmd_mwr_reg_byte(0xd068, 0x0800, 11, wr_val)
#define rd_eagle_tsc_cl72_ld_xmt_status_override()              _eagle_tsc_pmd_rde_field_byte(0xd068, 5, 15, __ERR)
#define wr_eagle_tsc_cl72_ld_xmt_status_override(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd068, 0x0400, 10, wr_val)
#define rd_eagle_tsc_cl72_ld_xmt_status_load()                  _eagle_tsc_pmd_rde_field_byte(0xd068, 6, 15, __ERR)
#define wr_eagle_tsc_cl72_ld_xmt_status_load(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd068, 0x0200, 9, wr_val)
#define rd_eagle_tsc_cl72_v2_constraint_dis()                   _eagle_tsc_pmd_rde_field_byte(0xd068, 7, 15, __ERR)
#define wr_eagle_tsc_cl72_v2_constraint_dis(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd068, 0x0100, 8, wr_val)
#define rd_eagle_tsc_cl72_tap_v2_val()                          _eagle_tsc_pmd_rde_field_byte(0xd068, 8, 10, __ERR)
#define wr_eagle_tsc_cl72_tap_v2_val(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd068, 0x00fc, 2, wr_val)
#define rd_eagle_tsc_cl72_inc_dec_val_sel()                     _eagle_tsc_pmd_rde_field_byte(0xd068, 14, 14, __ERR)
#define wr_eagle_tsc_cl72_inc_dec_val_sel(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd068, 0x0003, 0, wr_val)
#define rd_eagle_tsc_cl72_tx_dp_ln_clk_en()                     _eagle_tsc_pmd_rde_field_byte(0xd061, 13, 15, __ERR)
#define wr_eagle_tsc_cl72_tx_dp_ln_clk_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd061, 0x0004, 2, wr_val)
#define rd_eagle_tsc_cl72_signal_det_frc()                      _eagle_tsc_pmd_rde_field_byte(0xd061, 14, 15, __ERR)
#define wr_eagle_tsc_cl72_signal_det_frc(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd061, 0x0002, 1, wr_val)
#define rd_eagle_tsc_cl72_rx_trained()                          _eagle_tsc_pmd_rde_field_byte(0xd061, 15, 15, __ERR)
#define wr_eagle_tsc_cl72_rx_trained(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd061, 0x0001, 0, wr_val)
#define rd_eagle_tsc_cl72_frame_lock_rdy_for_cmd_en()           _eagle_tsc_pmd_rde_field_byte(0xd062, 14, 15, __ERR)
#define wr_eagle_tsc_cl72_frame_lock_rdy_for_cmd_en(wr_val)     _eagle_tsc_pmd_mwr_reg_byte(0xd062, 0x0002, 1, wr_val)
#define rd_eagle_tsc_cl72_brk_ring_osc()                        _eagle_tsc_pmd_rde_field_byte(0xd062, 15, 15, __ERR)
#define wr_eagle_tsc_cl72_brk_ring_osc(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd062, 0x0001, 0, wr_val)
#define rd_eagle_tsc_cl72_dis_max_wait_timer()                  _eagle_tsc_pmd_rde_field_byte(0xd063, 15, 15, __ERR)
#define wr_eagle_tsc_cl72_dis_max_wait_timer(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd063, 0x0001, 0, wr_val)
#define rd_eagle_tsc_cl72_ld_status_page()                      _eagle_tsc_pmd_rde_reg(0xd064, __ERR)
#define rd_eagle_tsc_cl72_ready_for_cmd()                       _eagle_tsc_pmd_rde_field_byte(0xd065, 15, 15, __ERR)
#define rd_eagle_tsc_cl72_tx_fir_tap_post_kr_init_val()         _eagle_tsc_pmd_rde_field_byte(0xd066, 5, 10, __ERR)
#define wr_eagle_tsc_cl72_tx_fir_tap_post_kr_init_val(wr_val)   _eagle_tsc_pmd_mwr_reg_byte(0xd066, 0x07e0, 5, wr_val)
#define rd_eagle_tsc_cl72_tx_fir_tap_pre_kr_init_val()          _eagle_tsc_pmd_rde_field_byte(0xd066, 11, 11, __ERR)
#define wr_eagle_tsc_cl72_tx_fir_tap_pre_kr_init_val(wr_val)    _eagle_tsc_pmd_mwr_reg_byte(0xd066, 0x001f, 0, wr_val)
#define rd_eagle_tsc_cl72_tx_fir_tap_main_kr_init_val()         _eagle_tsc_pmd_rde_field_byte(0xd067, 9, 9, __ERR)
#define wr_eagle_tsc_cl72_tx_fir_tap_main_kr_init_val(wr_val)   _eagle_tsc_pmd_mwr_reg_byte(0xd067, 0x007f, 0, wr_val)
#define rd_eagle_tsc_cl72_override_ld_status_page()             _eagle_tsc_pmd_rde_reg(0xd069, __ERR)
#define wr_eagle_tsc_cl72_override_ld_status_page(wr_val)       eagle_tsc_pmd_wr_reg(0xd069, wr_val)
#define rd_eagle_tsc_cl72_frame_lock_lh()                       _eagle_tsc_pmd_rde_field_byte(0xd06a, 4, 15, __ERR)
#define rd_eagle_tsc_cl72_ld_coeff_cmd_hist()                   _eagle_tsc_pmd_rde_field(0xd06a, 5, 5, __ERR)
#define rdc_eagle_tsc_revid_rev_letter()                        _eagle_tsc_pmd_rde_field_byte(0xd0f0, 0, 14, __ERR)
#define rdc_eagle_tsc_revid_rev_number()                        _eagle_tsc_pmd_rde_field_byte(0xd0f0, 2, 13, __ERR)
#define rdc_eagle_tsc_revid_bonding()                           _eagle_tsc_pmd_rde_field_byte(0xd0f0, 5, 14, __ERR)
#define rdc_eagle_tsc_revid_process()                           _eagle_tsc_pmd_rde_field_byte(0xd0f0, 7, 13, __ERR)
#define rdc_eagle_tsc_revid_model()                             _eagle_tsc_pmd_rde_field_byte(0xd0f0, 10, 10, __ERR)
#define rdc_eagle_tsc_revid_multiplicity()                      _eagle_tsc_pmd_rde_field_byte(0xd0fa, 0, 12, __ERR)
#define rdc_eagle_tsc_revid_mdio()                              _eagle_tsc_pmd_rde_field_byte(0xd0fa, 10, 15, __ERR)
#define rdc_eagle_tsc_revid_micro()                             _eagle_tsc_pmd_rde_field_byte(0xd0fa, 11, 15, __ERR)
#define rdc_eagle_tsc_revid_cl72()                              _eagle_tsc_pmd_rde_field_byte(0xd0fa, 12, 15, __ERR)
#define rdc_eagle_tsc_revid_pir()                               _eagle_tsc_pmd_rde_field_byte(0xd0fa, 13, 15, __ERR)
#define rdc_eagle_tsc_revid_llp()                               _eagle_tsc_pmd_rde_field_byte(0xd0fa, 14, 15, __ERR)
#define rdc_eagle_tsc_revid_eee()                               _eagle_tsc_pmd_rde_field_byte(0xd0fa, 15, 15, __ERR)
#define rdc_eagle_tsc_revid2()                                  _eagle_tsc_pmd_rde_field_byte(0xd0fe, 12, 12, __ERR)
#define rdc_eagle_tsc_core_s_rstb()                             _eagle_tsc_pmd_rde_field_byte(0xd0f1, 15, 15, __ERR)
#define wrc_eagle_tsc_core_s_rstb(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0f1, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_loop_filter_stable()                _eagle_tsc_pmd_rde_field_byte(0xd0f2, 1, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_loop_filter_stable(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_afe_s_pll_reset_frc()                     _eagle_tsc_pmd_rde_field_byte(0xd0f2, 2, 15, __ERR)
#define wrc_eagle_tsc_afe_s_pll_reset_frc(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x2000, 13, wr_val)
#define rdc_eagle_tsc_afe_s_pll_reset_frc_val()                 _eagle_tsc_pmd_rde_field_byte(0xd0f2, 3, 15, __ERR)
#define wrc_eagle_tsc_afe_s_pll_reset_frc_val(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x1000, 12, wr_val)
#define rdc_eagle_tsc_tx_s_clkgate_frc_on()                     _eagle_tsc_pmd_rde_field_byte(0xd0f2, 4, 15, __ERR)
#define wrc_eagle_tsc_tx_s_clkgate_frc_on(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_tx_s_comclk_frc_on()                      _eagle_tsc_pmd_rde_field_byte(0xd0f2, 5, 15, __ERR)
#define wrc_eagle_tsc_tx_s_comclk_frc_on(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_tx_s_comclk_sel()                         _eagle_tsc_pmd_rde_field_byte(0xd0f2, 6, 15, __ERR)
#define wrc_eagle_tsc_tx_s_comclk_sel(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0200, 9, wr_val)
#define rdc_eagle_tsc_pmd_tx_clk_vld_frc_val()                  _eagle_tsc_pmd_rde_field_byte(0xd0f2, 7, 15, __ERR)
#define wrc_eagle_tsc_pmd_tx_clk_vld_frc_val(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0100, 8, wr_val)
#define rdc_eagle_tsc_pmd_tx_clk_vld_frc()                      _eagle_tsc_pmd_rde_field_byte(0xd0f2, 8, 15, __ERR)
#define wrc_eagle_tsc_pmd_tx_clk_vld_frc(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_pmd_mdio_trans_pkill()                    _eagle_tsc_pmd_rde_field_byte(0xd0f2, 10, 15, __ERR)
#define wrc_eagle_tsc_pmd_mdio_trans_pkill(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_sup_rst_seq_frc()                         _eagle_tsc_pmd_rde_field_byte(0xd0f2, 11, 15, __ERR)
#define wrc_eagle_tsc_sup_rst_seq_frc(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_sup_rst_seq_frc_val()                     _eagle_tsc_pmd_rde_field_byte(0xd0f2, 12, 15, __ERR)
#define wrc_eagle_tsc_sup_rst_seq_frc_val(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_pmd_core_dp_h_rstb_pkill()                _eagle_tsc_pmd_rde_field_byte(0xd0f2, 14, 15, __ERR)
#define wrc_eagle_tsc_pmd_core_dp_h_rstb_pkill(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd0f2, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_core_multicast_mask_control()             _eagle_tsc_pmd_rde_field_byte(0xd0f3, 12, 12, __ERR)
#define wrc_eagle_tsc_core_multicast_mask_control(wr_val)       _eagle_tsc_pmd_mwr_reg_byte(0xd0f3, 0x000f, 0, wr_val)
#define rdc_eagle_tsc_uc_active()                               _eagle_tsc_pmd_rde_field_byte(0xd0f4, 0, 15, __ERR)
#define wrc_eagle_tsc_uc_active(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd0f4, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_afe_s_pll_pwrdn()                         _eagle_tsc_pmd_rde_field_byte(0xd0f4, 1, 15, __ERR)
#define wrc_eagle_tsc_afe_s_pll_pwrdn(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0f4, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_core_dp_s_rstb()                          _eagle_tsc_pmd_rde_field_byte(0xd0f4, 2, 15, __ERR)
#define wrc_eagle_tsc_core_dp_s_rstb(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd0f4, 0x2000, 13, wr_val)
#define rdc_eagle_tsc_heartbeat_count_1us()                     _eagle_tsc_pmd_rde_field(0xd0f4, 6, 6, __ERR)
#define wrc_eagle_tsc_heartbeat_count_1us(wr_val)               eagle_tsc_pmd_mwr_reg(0xd0f4, 0x03ff, 0, wr_val)
#define rdc_eagle_tsc_uc_ack_core_dp_reset()                    _eagle_tsc_pmd_rde_field_byte(0xd0f5, 14, 15, __ERR)
#define wrc_eagle_tsc_uc_ack_core_dp_reset(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0f5, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_uc_ack_core_cfg_done()                    _eagle_tsc_pmd_rde_field_byte(0xd0f5, 15, 15, __ERR)
#define wrc_eagle_tsc_uc_ack_core_cfg_done(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0f5, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_lane_reset_released()                     _eagle_tsc_pmd_rde_field_byte(0xd0f8, 1, 15, __ERR)
#define rdc_eagle_tsc_lane_reset_released_index()               _eagle_tsc_pmd_rde_field_byte(0xd0f8, 3, 11, __ERR)
#define rdc_eagle_tsc_core_dp_reset_state()                     _eagle_tsc_pmd_rde_field_byte(0xd0f8, 13, 13, __ERR)
#define rdc_eagle_tsc_core_reg_reset_occurred()                 _eagle_tsc_pmd_rde_field_byte(0xd0f6, 15, 15, __ERR)
#define wrc_eagle_tsc_core_reg_reset_occurred(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd0f6, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_rst_seq_dis_flt_mode()                    _eagle_tsc_pmd_rde_field_byte(0xd0f7, 0, 14, __ERR)
#define wrc_eagle_tsc_rst_seq_dis_flt_mode(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0f7, 0xc000, 14, wr_val)
#define rdc_eagle_tsc_pwrdn_seq_timer()                         _eagle_tsc_pmd_rde_field_byte(0xd0f7, 5, 13, __ERR)
#define wrc_eagle_tsc_pwrdn_seq_timer(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0f7, 0x0700, 8, wr_val)
#define rdc_eagle_tsc_rst_seq_timer()                           _eagle_tsc_pmd_rde_field_byte(0xd0f7, 13, 13, __ERR)
#define wrc_eagle_tsc_rst_seq_timer(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0f7, 0x0007, 0, wr_val)
#define rdc_eagle_tsc_pmd_core_mode()                           _eagle_tsc_pmd_rde_reg(0xd0f9, __ERR)
#define rdc_eagle_tsc_tx_lane_map_2()                           _eagle_tsc_pmd_rde_field_byte(0xd0fb, 1, 11, __ERR)
#define wrc_eagle_tsc_tx_lane_map_2(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0fb, 0x7c00, 10, wr_val)
#define rdc_eagle_tsc_tx_lane_map_1()                           _eagle_tsc_pmd_rde_field_byte(0xd0fb, 6, 11, __ERR)
#define wrc_eagle_tsc_tx_lane_map_1(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0fb, 0x03e0, 5, wr_val)
#define rdc_eagle_tsc_tx_lane_map_0()                           _eagle_tsc_pmd_rde_field_byte(0xd0fb, 11, 11, __ERR)
#define wrc_eagle_tsc_tx_lane_map_0(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0fb, 0x001f, 0, wr_val)
#define rdc_eagle_tsc_lane_addr_1()                             _eagle_tsc_pmd_rde_field_byte(0xd0fc, 1, 11, __ERR)
#define wrc_eagle_tsc_lane_addr_1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0fc, 0x7c00, 10, wr_val)
#define rdc_eagle_tsc_lane_addr_0()                             _eagle_tsc_pmd_rde_field_byte(0xd0fc, 6, 11, __ERR)
#define wrc_eagle_tsc_lane_addr_0(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0fc, 0x03e0, 5, wr_val)
#define rdc_eagle_tsc_tx_lane_map_3()                           _eagle_tsc_pmd_rde_field_byte(0xd0fc, 11, 11, __ERR)
#define wrc_eagle_tsc_tx_lane_map_3(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0fc, 0x001f, 0, wr_val)
#define rdc_eagle_tsc_lane_addr_3()                             _eagle_tsc_pmd_rde_field_byte(0xd0fd, 3, 11, __ERR)
#define wrc_eagle_tsc_lane_addr_3(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0fd, 0x1f00, 8, wr_val)
#define rdc_eagle_tsc_lane_addr_2()                             _eagle_tsc_pmd_rde_field_byte(0xd0fd, 11, 11, __ERR)
#define wrc_eagle_tsc_lane_addr_2(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0fd, 0x001f, 0, wr_val)
#define rd_eagle_tsc_cdr_integ_reg()                            _eagle_tsc_pmd_rde_field_signed(0xd005, 0, 0, __ERR)
#define rd_eagle_tsc_cdr_lm_outoflock()                         _eagle_tsc_pmd_rde_field_byte(0xd006, 7, 15, __ERR)
#define rd_eagle_tsc_cdr_phase_err()                            _eagle_tsc_pmd_rde_field_signed_byte(0xd006, 11, 11, __ERR)
#define rd_eagle_tsc_cnt_bin_p1_dreg()                          _eagle_tsc_pmd_rde_field_byte(0xd007, 1, 9, __ERR)
#define rd_eagle_tsc_cnt_bin_d_dreg()                           _eagle_tsc_pmd_rde_field_byte(0xd007, 9, 9, __ERR)
#define rd_eagle_tsc_cnt_bin_m1_preg()                          _eagle_tsc_pmd_rde_field_byte(0xd008, 1, 9, __ERR)
#define rd_eagle_tsc_cnt_bin_p1_preg()                          _eagle_tsc_pmd_rde_field_byte(0xd008, 9, 9, __ERR)
#define rd_eagle_tsc_cnt_bin_d_mreg()                           _eagle_tsc_pmd_rde_field_byte(0xd009, 1, 9, __ERR)
#define rd_eagle_tsc_cnt_bin_m1_mreg()                          _eagle_tsc_pmd_rde_field_byte(0xd009, 9, 9, __ERR)
#define rd_eagle_tsc_cnt_d_minus_p1()                           _eagle_tsc_pmd_rde_field_signed_byte(0xd00a, 0, 8, __ERR)
#define rd_eagle_tsc_cnt_d_minus_m1()                           _eagle_tsc_pmd_rde_field_signed_byte(0xd00a, 8, 8, __ERR)
#define rd_eagle_tsc_cdr_lm_thr_sel()                           _eagle_tsc_pmd_rde_field_byte(0xd001, 5, 13, __ERR)
#define wr_eagle_tsc_cdr_lm_thr_sel(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0700, 8, wr_val)
#define rd_eagle_tsc_cdr_freq_override_en()                     _eagle_tsc_pmd_rde_field_byte(0xd001, 8, 15, __ERR)
#define wr_eagle_tsc_cdr_freq_override_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0080, 7, wr_val)
#define rd_eagle_tsc_cdr_integ_sat_sel()                        _eagle_tsc_pmd_rde_field_byte(0xd001, 9, 15, __ERR)
#define wr_eagle_tsc_cdr_integ_sat_sel(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0040, 6, wr_val)
#define rd_eagle_tsc_cdr_phase_err_frz()                        _eagle_tsc_pmd_rde_field_byte(0xd001, 10, 15, __ERR)
#define wr_eagle_tsc_cdr_phase_err_frz(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0020, 5, wr_val)
#define rd_eagle_tsc_cdr_integ_reg_clr()                        _eagle_tsc_pmd_rde_field_byte(0xd001, 11, 15, __ERR)
#define wr_eagle_tsc_cdr_integ_reg_clr(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0010, 4, wr_val)
#define rd_eagle_tsc_cdr_freq_en()                              _eagle_tsc_pmd_rde_field_byte(0xd001, 13, 15, __ERR)
#define wr_eagle_tsc_cdr_freq_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0004, 2, wr_val)
#define rd_eagle_tsc_br_pd_en()                                 _eagle_tsc_pmd_rde_field_byte(0xd001, 14, 15, __ERR)
#define wr_eagle_tsc_br_pd_en(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0002, 1, wr_val)
#define rd_eagle_tsc_cdr_phase_sat_ctrl()                       _eagle_tsc_pmd_rde_field_byte(0xd001, 15, 15, __ERR)
#define wr_eagle_tsc_cdr_phase_sat_ctrl(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd001, 0x0001, 0, wr_val)
#define rd_eagle_tsc_cdr_freq_override_val()                    _eagle_tsc_pmd_rde_field_signed(0xd002, 0, 1, __ERR)
#define wr_eagle_tsc_cdr_freq_override_val(wr_val)              eagle_tsc_pmd_mwr_reg(0xd002, 0xfffe, 1, wr_val)
#define rd_eagle_tsc_dfe_vga_unfreeze()                         _eagle_tsc_pmd_rde_field_byte(0xd002, 15, 15, __ERR)
#define wr_eagle_tsc_dfe_vga_unfreeze(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd002, 0x0001, 0, wr_val)
#define rd_eagle_tsc_osx2p_pherr_gain()                         _eagle_tsc_pmd_rde_field_byte(0xd003, 6, 14, __ERR)
#define wr_eagle_tsc_osx2p_pherr_gain(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd003, 0x0300, 8, wr_val)
#define rd_eagle_tsc_pattern_sel()                              _eagle_tsc_pmd_rde_field_byte(0xd003, 8, 12, __ERR)
#define wr_eagle_tsc_pattern_sel(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd003, 0x00f0, 4, wr_val)
#define rd_eagle_tsc_phase_err_offset_mult_2()                  _eagle_tsc_pmd_rde_field_byte(0xd003, 14, 15, __ERR)
#define wr_eagle_tsc_phase_err_offset_mult_2(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd003, 0x0002, 1, wr_val)
#define rd_eagle_tsc_cdr_zero_polarity()                        _eagle_tsc_pmd_rde_field_byte(0xd003, 15, 15, __ERR)
#define wr_eagle_tsc_cdr_zero_polarity(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd003, 0x0001, 0, wr_val)
#define rd_eagle_tsc_send_lms_to_pcs()                          _eagle_tsc_pmd_rde_field_byte(0xd00b, 1, 15, __ERR)
#define wr_eagle_tsc_send_lms_to_pcs(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd00b, 0x4000, 14, wr_val)
#define rd_eagle_tsc_rx_pi_manual_reset()                       _eagle_tsc_pmd_rde_field_byte(0xd004, 0, 15, __ERR)
#define wr_eagle_tsc_rx_pi_manual_reset(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd004, 0x8000, 15, wr_val)
#define rd_eagle_tsc_rx_pi_slicers_en()                         _eagle_tsc_pmd_rde_field_byte(0xd004, 1, 13, __ERR)
#define wr_eagle_tsc_rx_pi_slicers_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd004, 0x7000, 12, wr_val)
#define rd_eagle_tsc_rx_pi_manual_mode()                        _eagle_tsc_pmd_rde_field_byte(0xd004, 4, 15, __ERR)
#define wr_eagle_tsc_rx_pi_manual_mode(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd004, 0x0800, 11, wr_val)
#define rd_eagle_tsc_rx_pi_phase_step_dir()                     _eagle_tsc_pmd_rde_field_byte(0xd004, 5, 15, __ERR)
#define wr_eagle_tsc_rx_pi_phase_step_dir(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd004, 0x0400, 10, wr_val)
#define rd_eagle_tsc_rx_pi_manual_strobe()                      _eagle_tsc_pmd_rde_field_byte(0xd004, 6, 15, __ERR)
#define wr_eagle_tsc_rx_pi_manual_strobe(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd004, 0x0200, 9, wr_val)
#define rd_eagle_tsc_rx_pi_phase_step_cnt()                     _eagle_tsc_pmd_rde_field_byte(0xd004, 9, 9, __ERR)
#define wr_eagle_tsc_rx_pi_phase_step_cnt(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd004, 0x007f, 0, wr_val)
#define rd_eagle_tsc_uc_dsc_supp_info()                         _eagle_tsc_pmd_rde_field_byte(0xd00d, 0, 8, __ERR)
#define wr_eagle_tsc_uc_dsc_supp_info(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd00d, 0xff00, 8, wr_val)
#define rd_eagle_tsc_uc_dsc_ready_for_cmd()                     _eagle_tsc_pmd_rde_field_byte(0xd00d, 8, 15, __ERR)
#define wr_eagle_tsc_uc_dsc_ready_for_cmd(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd00d, 0x0080, 7, wr_val)
#define rd_eagle_tsc_uc_dsc_error_found()                       _eagle_tsc_pmd_rde_field_byte(0xd00d, 9, 15, __ERR)
#define wr_eagle_tsc_uc_dsc_error_found(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd00d, 0x0040, 6, wr_val)
#define rd_eagle_tsc_uc_dsc_gp_uc_req()                         _eagle_tsc_pmd_rde_field_byte(0xd00d, 10, 10, __ERR)
#define wr_eagle_tsc_uc_dsc_gp_uc_req(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd00d, 0x003f, 0, wr_val)
#define rd_eagle_tsc_uc_dsc_data()                              _eagle_tsc_pmd_rde_reg(0xd00e, __ERR)
#define wr_eagle_tsc_uc_dsc_data(wr_val)                        eagle_tsc_pmd_wr_reg(0xd00e, wr_val)
#define rd_eagle_tsc_eee_mode_en()                              _eagle_tsc_pmd_rde_field_byte(0xd010, 14, 15, __ERR)
#define wr_eagle_tsc_eee_mode_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0002, 1, wr_val)
#define rd_eagle_tsc_eee_quiet_rx_afe_pwrdwn_val()              _eagle_tsc_pmd_rde_field_byte(0xd010, 13, 15, __ERR)
#define wr_eagle_tsc_eee_quiet_rx_afe_pwrdwn_val(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ignore_rx_mode()                           _eagle_tsc_pmd_rde_field_byte(0xd010, 12, 15, __ERR)
#define wr_eagle_tsc_ignore_rx_mode(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0008, 3, wr_val)
#define rd_eagle_tsc_cl72_timer_en()                            _eagle_tsc_pmd_rde_field_byte(0xd010, 11, 15, __ERR)
#define wr_eagle_tsc_cl72_timer_en(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0010, 4, wr_val)
#define rd_eagle_tsc_uc_tune_en()                               _eagle_tsc_pmd_rde_field_byte(0xd010, 10, 15, __ERR)
#define wr_eagle_tsc_uc_tune_en(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0020, 5, wr_val)
#define rd_eagle_tsc_hw_tune_en()                               _eagle_tsc_pmd_rde_field_byte(0xd010, 9, 15, __ERR)
#define wr_eagle_tsc_hw_tune_en(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0040, 6, wr_val)
#define rd_eagle_tsc_uc_trnsum_en()                             _eagle_tsc_pmd_rde_field_byte(0xd010, 8, 15, __ERR)
#define wr_eagle_tsc_uc_trnsum_en(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0080, 7, wr_val)
#define rd_eagle_tsc_eee_measure_en()                           _eagle_tsc_pmd_rde_field_byte(0xd010, 7, 15, __ERR)
#define wr_eagle_tsc_eee_measure_en(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0100, 8, wr_val)
#define rd_eagle_tsc_uc_ack_dsc_eee_done()                      _eagle_tsc_pmd_rde_field_byte(0xd010, 4, 15, __ERR)
#define wr_eagle_tsc_uc_ack_dsc_eee_done(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x0800, 11, wr_val)
#define rd_eagle_tsc_uc_ack_dsc_reset()                         _eagle_tsc_pmd_rde_field_byte(0xd010, 3, 15, __ERR)
#define wr_eagle_tsc_uc_ack_dsc_reset(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x1000, 12, wr_val)
#define rd_eagle_tsc_uc_ack_dsc_restart()                       _eagle_tsc_pmd_rde_field_byte(0xd010, 2, 15, __ERR)
#define wr_eagle_tsc_uc_ack_dsc_restart(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x2000, 13, wr_val)
#define rd_eagle_tsc_uc_ack_dsc_config()                        _eagle_tsc_pmd_rde_field_byte(0xd010, 1, 15, __ERR)
#define wr_eagle_tsc_uc_ack_dsc_config(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x4000, 14, wr_val)
#define rd_eagle_tsc_set_meas_incomplete()                      _eagle_tsc_pmd_rde_field_byte(0xd010, 0, 15, __ERR)
#define wr_eagle_tsc_set_meas_incomplete(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd010, 0x8000, 15, wr_val)
#define rd_eagle_tsc_rx_dsc_lock_frc()                          _eagle_tsc_pmd_rde_field_byte(0xd011, 15, 15, __ERR)
#define wr_eagle_tsc_rx_dsc_lock_frc(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0001, 0, wr_val)
#define rd_eagle_tsc_rx_dsc_lock_frc_val()                      _eagle_tsc_pmd_rde_field_byte(0xd011, 14, 15, __ERR)
#define wr_eagle_tsc_rx_dsc_lock_frc_val(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0002, 1, wr_val)
#define rd_eagle_tsc_dsc_clr_frc()                              _eagle_tsc_pmd_rde_field_byte(0xd011, 13, 15, __ERR)
#define wr_eagle_tsc_dsc_clr_frc(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0004, 2, wr_val)
#define rd_eagle_tsc_dsc_clr_frc_val()                          _eagle_tsc_pmd_rde_field_byte(0xd011, 12, 15, __ERR)
#define wr_eagle_tsc_dsc_clr_frc_val(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0008, 3, wr_val)
#define rd_eagle_tsc_trnsum_frz_frc()                           _eagle_tsc_pmd_rde_field_byte(0xd011, 11, 15, __ERR)
#define wr_eagle_tsc_trnsum_frz_frc(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0010, 4, wr_val)
#define rd_eagle_tsc_trnsum_frz_frc_val()                       _eagle_tsc_pmd_rde_field_byte(0xd011, 10, 15, __ERR)
#define wr_eagle_tsc_trnsum_frz_frc_val(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0020, 5, wr_val)
#define rd_eagle_tsc_timer_done_frc()                           _eagle_tsc_pmd_rde_field_byte(0xd011, 9, 15, __ERR)
#define wr_eagle_tsc_timer_done_frc(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0040, 6, wr_val)
#define rd_eagle_tsc_timer_done_frc_val()                       _eagle_tsc_pmd_rde_field_byte(0xd011, 8, 15, __ERR)
#define wr_eagle_tsc_timer_done_frc_val(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0080, 7, wr_val)
#define rd_eagle_tsc_freq_upd_en_frc()                          _eagle_tsc_pmd_rde_field_byte(0xd011, 7, 15, __ERR)
#define wr_eagle_tsc_freq_upd_en_frc(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0100, 8, wr_val)
#define rd_eagle_tsc_freq_upd_en_frc_val()                      _eagle_tsc_pmd_rde_field_byte(0xd011, 6, 15, __ERR)
#define wr_eagle_tsc_freq_upd_en_frc_val(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0200, 9, wr_val)
#define rd_eagle_tsc_cdr_frz_frc()                              _eagle_tsc_pmd_rde_field_byte(0xd011, 5, 15, __ERR)
#define wr_eagle_tsc_cdr_frz_frc(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0400, 10, wr_val)
#define rd_eagle_tsc_cdr_frz_frc_val()                          _eagle_tsc_pmd_rde_field_byte(0xd011, 4, 15, __ERR)
#define wr_eagle_tsc_cdr_frz_frc_val(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x0800, 11, wr_val)
#define rd_eagle_tsc_trnsum_clr_frc()                           _eagle_tsc_pmd_rde_field_byte(0xd011, 3, 15, __ERR)
#define wr_eagle_tsc_trnsum_clr_frc(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x1000, 12, wr_val)
#define rd_eagle_tsc_trnsum_clr_frc_val()                       _eagle_tsc_pmd_rde_field_byte(0xd011, 2, 15, __ERR)
#define wr_eagle_tsc_trnsum_clr_frc_val(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd011, 0x2000, 13, wr_val)
#define rd_eagle_tsc_eee_lfsr_cnt()                             _eagle_tsc_pmd_rde_field(0xd012, 3, 3, __ERR)
#define wr_eagle_tsc_eee_lfsr_cnt(wr_val)                       eagle_tsc_pmd_mwr_reg(0xd012, 0x1fff, 0, wr_val)
#define rd_eagle_tsc_measure_lfsr_cnt()                         _eagle_tsc_pmd_rde_field(0xd013, 3, 3, __ERR)
#define wr_eagle_tsc_measure_lfsr_cnt(wr_val)                   eagle_tsc_pmd_mwr_reg(0xd013, 0x1fff, 0, wr_val)
#define rd_eagle_tsc_acq_cdr_timeout()                          _eagle_tsc_pmd_rde_field_byte(0xd014, 11, 11, __ERR)
#define wr_eagle_tsc_acq_cdr_timeout(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd014, 0x001f, 0, wr_val)
#define rd_eagle_tsc_cdr_settle_timeout()                       _eagle_tsc_pmd_rde_field_byte(0xd014, 6, 11, __ERR)
#define wr_eagle_tsc_cdr_settle_timeout(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd014, 0x03e0, 5, wr_val)
#define rd_eagle_tsc_hw_tune_timeout()                          _eagle_tsc_pmd_rde_field_byte(0xd014, 1, 11, __ERR)
#define wr_eagle_tsc_hw_tune_timeout(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd014, 0x7c00, 10, wr_val)
#define rd_eagle_tsc_measure_timeout()                          _eagle_tsc_pmd_rde_field_byte(0xd015, 11, 11, __ERR)
#define wr_eagle_tsc_measure_timeout(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd015, 0x001f, 0, wr_val)
#define rd_eagle_tsc_eee_acq_cdr_timeout()                      _eagle_tsc_pmd_rde_field_byte(0xd015, 6, 11, __ERR)
#define wr_eagle_tsc_eee_acq_cdr_timeout(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd015, 0x03e0, 5, wr_val)
#define rd_eagle_tsc_eee_cdr_settle_timeout()                   _eagle_tsc_pmd_rde_field_byte(0xd015, 1, 11, __ERR)
#define wr_eagle_tsc_eee_cdr_settle_timeout(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd015, 0x7c00, 10, wr_val)
#define rd_eagle_tsc_eee_hw_tune_timeout()                      _eagle_tsc_pmd_rde_field_byte(0xd016, 11, 11, __ERR)
#define wr_eagle_tsc_eee_hw_tune_timeout(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd016, 0x001f, 0, wr_val)
#define rd_eagle_tsc_eee_ana_pwr_timeout()                      _eagle_tsc_pmd_rde_field_byte(0xd016, 1, 11, __ERR)
#define wr_eagle_tsc_eee_ana_pwr_timeout(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd016, 0x7c00, 10, wr_val)
#define rd_eagle_tsc_cdr_bwsel_integ_acqcdr()                   _eagle_tsc_pmd_rde_field_byte(0xd017, 12, 12, __ERR)
#define wr_eagle_tsc_cdr_bwsel_integ_acqcdr(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd017, 0x000f, 0, wr_val)
#define rd_eagle_tsc_cdr_bwsel_integ_eee_acqcdr()               _eagle_tsc_pmd_rde_field_byte(0xd017, 8, 12, __ERR)
#define wr_eagle_tsc_cdr_bwsel_integ_eee_acqcdr(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd017, 0x00f0, 4, wr_val)
#define rd_eagle_tsc_cdr_bwsel_integ_norm()                     _eagle_tsc_pmd_rde_field_byte(0xd017, 4, 12, __ERR)
#define wr_eagle_tsc_cdr_bwsel_integ_norm(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd017, 0x0f00, 8, wr_val)
#define rd_eagle_tsc_cdr_bwsel_prop_acqcdr()                    _eagle_tsc_pmd_rde_field_byte(0xd017, 2, 14, __ERR)
#define wr_eagle_tsc_cdr_bwsel_prop_acqcdr(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd017, 0x3000, 12, wr_val)
#define rd_eagle_tsc_cdr_bwsel_prop_norm()                      _eagle_tsc_pmd_rde_field_byte(0xd017, 0, 14, __ERR)
#define wr_eagle_tsc_cdr_bwsel_prop_norm(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd017, 0xc000, 14, wr_val)
#define rd_eagle_tsc_phase_err_offset()                         _eagle_tsc_pmd_rde_field_signed_byte(0xd018, 12, 12, __ERR)
#define wr_eagle_tsc_phase_err_offset(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd018, 0x000f, 0, wr_val)
#define rd_eagle_tsc_eee_phase_err_offset()                     _eagle_tsc_pmd_rde_field_signed_byte(0xd018, 8, 12, __ERR)
#define wr_eagle_tsc_eee_phase_err_offset(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd018, 0x00f0, 4, wr_val)
#define rd_eagle_tsc_phase_err_offset_en()                      _eagle_tsc_pmd_rde_field_byte(0xd018, 6, 14, __ERR)
#define wr_eagle_tsc_phase_err_offset_en(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd018, 0x0300, 8, wr_val)
#define rd_eagle_tsc_eee_phase_err_offset_en()                  _eagle_tsc_pmd_rde_field_byte(0xd018, 4, 14, __ERR)
#define wr_eagle_tsc_eee_phase_err_offset_en(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd018, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_cdr_bwsel_prop_eee_acqcdr()                _eagle_tsc_pmd_rde_field_byte(0xd018, 0, 14, __ERR)
#define wr_eagle_tsc_cdr_bwsel_prop_eee_acqcdr(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd018, 0xc000, 14, wr_val)
#define rd_eagle_tsc_rx_restart_pmd()                           _eagle_tsc_pmd_rde_field_byte(0xd019, 15, 15, __ERR)
#define wr_eagle_tsc_rx_restart_pmd(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd019, 0x0001, 0, wr_val)
#define rd_eagle_tsc_rx_restart_pmd_hold()                      _eagle_tsc_pmd_rde_field_byte(0xd019, 14, 15, __ERR)
#define wr_eagle_tsc_rx_restart_pmd_hold(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd019, 0x0002, 1, wr_val)
#define rd_eagle_tsc_dsc_state_one_hot()                        _eagle_tsc_pmd_rde_field(0xd01b, 6, 6, __ERR)
#define rd_eagle_tsc_dsc_state_eee_one_hot()                    _eagle_tsc_pmd_rde_field_byte(0xd01c, 9, 9, __ERR)
#define rd_eagle_tsc_restart_pi_ext_mode()                      _eagle_tsc_pmd_rde_field_byte(0xd01d, 15, 15, __ERR)
#define rd_eagle_tsc_restart_sigdet()                           _eagle_tsc_pmd_rde_field_byte(0xd01d, 14, 15, __ERR)
#define rd_eagle_tsc_restart_pmd_restart()                      _eagle_tsc_pmd_rde_field_byte(0xd01d, 13, 15, __ERR)
#define rd_eagle_tsc_eee_quiet_from_eee_states()                _eagle_tsc_pmd_rde_field_byte(0xd01d, 12, 15, __ERR)
#define rd_eagle_tsc_dsc_state()                                _eagle_tsc_pmd_rde_field_byte(0xd01e, 0, 11, __ERR)
#define rd_eagle_tsc_dsc_sm_gp_uc_req()                         _eagle_tsc_pmd_rde_field_byte(0xd01e, 5, 10, __ERR)
#define rd_eagle_tsc_dsc_sm_ready_for_cmd()                     _eagle_tsc_pmd_rde_field_byte(0xd01e, 11, 15, __ERR)
#define rd_eagle_tsc_dsc_sm_scratch()                           _eagle_tsc_pmd_rde_field_byte(0xd01e, 12, 12, __ERR)
#define rd_eagle_tsc_eee_measure_cnt()                          _eagle_tsc_pmd_rde_field(0xd01a, 0, 7, __ERR)
#define rd_eagle_tsc_meas_incomplete()                          _eagle_tsc_pmd_rde_field_byte(0xd01a, 14, 15, __ERR)
#define rd_eagle_tsc_rx_dsc_lock()                              _eagle_tsc_pmd_rde_field_byte(0xd01a, 15, 15, __ERR)
#define rd_eagle_tsc_dfe_1_en()                                 _eagle_tsc_pmd_rde_field_byte(0xd021, 0, 15, __ERR)
#define wr_eagle_tsc_dfe_1_en(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x8000, 15, wr_val)
#define rd_eagle_tsc_dfe_1_err_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd021, 1, 14, __ERR)
#define wr_eagle_tsc_dfe_1_err_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x6000, 13, wr_val)
#define rd_eagle_tsc_dfe_1_gradient_invert()                    _eagle_tsc_pmd_rde_field_byte(0xd021, 3, 15, __ERR)
#define wr_eagle_tsc_dfe_1_gradient_invert(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x1000, 12, wr_val)
#define rd_eagle_tsc_dfe_1_err_gain()                           _eagle_tsc_pmd_rde_field_byte(0xd021, 4, 14, __ERR)
#define wr_eagle_tsc_dfe_1_err_gain(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_dfe_1_inv_m1()                             _eagle_tsc_pmd_rde_field_byte(0xd021, 6, 15, __ERR)
#define wr_eagle_tsc_dfe_1_inv_m1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x0200, 9, wr_val)
#define rd_eagle_tsc_dfe_1_inv_p1()                             _eagle_tsc_pmd_rde_field_byte(0xd021, 7, 15, __ERR)
#define wr_eagle_tsc_dfe_1_inv_p1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x0100, 8, wr_val)
#define rd_eagle_tsc_dfe_1_cmn_only()                           _eagle_tsc_pmd_rde_field_byte(0xd021, 14, 15, __ERR)
#define wr_eagle_tsc_dfe_1_cmn_only(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x0002, 1, wr_val)
#define rd_eagle_tsc_dfe_1_acc_clr()                            _eagle_tsc_pmd_rde_field_byte(0xd021, 15, 15, __ERR)
#define wr_eagle_tsc_dfe_1_acc_clr(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd021, 0x0001, 0, wr_val)
#define rd_eagle_tsc_dfe_1_pattern_bit_en()                     _eagle_tsc_pmd_rde_field_byte(0xd022, 2, 10, __ERR)
#define wr_eagle_tsc_dfe_1_pattern_bit_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd022, 0x3f00, 8, wr_val)
#define rd_eagle_tsc_dfe_1_pattern()                            _eagle_tsc_pmd_rde_field_byte(0xd022, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_1_pattern(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd022, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_2_en()                                 _eagle_tsc_pmd_rde_field_byte(0xd023, 0, 15, __ERR)
#define wr_eagle_tsc_dfe_2_en(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x8000, 15, wr_val)
#define rd_eagle_tsc_dfe_2_err_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd023, 1, 14, __ERR)
#define wr_eagle_tsc_dfe_2_err_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x6000, 13, wr_val)
#define rd_eagle_tsc_dfe_2_gradient_invert()                    _eagle_tsc_pmd_rde_field_byte(0xd023, 3, 15, __ERR)
#define wr_eagle_tsc_dfe_2_gradient_invert(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x1000, 12, wr_val)
#define rd_eagle_tsc_dfe_2_err_gain()                           _eagle_tsc_pmd_rde_field_byte(0xd023, 4, 14, __ERR)
#define wr_eagle_tsc_dfe_2_err_gain(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_dfe_2_inv_m1()                             _eagle_tsc_pmd_rde_field_byte(0xd023, 6, 15, __ERR)
#define wr_eagle_tsc_dfe_2_inv_m1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x0200, 9, wr_val)
#define rd_eagle_tsc_dfe_2_inv_p1()                             _eagle_tsc_pmd_rde_field_byte(0xd023, 7, 15, __ERR)
#define wr_eagle_tsc_dfe_2_inv_p1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x0100, 8, wr_val)
#define rd_eagle_tsc_dfe_2_cmn_only()                           _eagle_tsc_pmd_rde_field_byte(0xd023, 14, 15, __ERR)
#define wr_eagle_tsc_dfe_2_cmn_only(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x0002, 1, wr_val)
#define rd_eagle_tsc_dfe_2_acc_clr()                            _eagle_tsc_pmd_rde_field_byte(0xd023, 15, 15, __ERR)
#define wr_eagle_tsc_dfe_2_acc_clr(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd023, 0x0001, 0, wr_val)
#define rd_eagle_tsc_dfe_2_pattern_bit_en()                     _eagle_tsc_pmd_rde_field_byte(0xd024, 2, 10, __ERR)
#define wr_eagle_tsc_dfe_2_pattern_bit_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd024, 0x3f00, 8, wr_val)
#define rd_eagle_tsc_dfe_2_pattern()                            _eagle_tsc_pmd_rde_field_byte(0xd024, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_2_pattern(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd024, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_3_en()                                 _eagle_tsc_pmd_rde_field_byte(0xd025, 0, 15, __ERR)
#define wr_eagle_tsc_dfe_3_en(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd025, 0x8000, 15, wr_val)
#define rd_eagle_tsc_dfe_3_err_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd025, 1, 14, __ERR)
#define wr_eagle_tsc_dfe_3_err_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd025, 0x6000, 13, wr_val)
#define rd_eagle_tsc_dfe_3_gradient_invert()                    _eagle_tsc_pmd_rde_field_byte(0xd025, 3, 15, __ERR)
#define wr_eagle_tsc_dfe_3_gradient_invert(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd025, 0x1000, 12, wr_val)
#define rd_eagle_tsc_dfe_3_err_gain()                           _eagle_tsc_pmd_rde_field_byte(0xd025, 4, 14, __ERR)
#define wr_eagle_tsc_dfe_3_err_gain(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd025, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_dfe_3_inv_m1()                             _eagle_tsc_pmd_rde_field_byte(0xd025, 6, 15, __ERR)
#define wr_eagle_tsc_dfe_3_inv_m1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd025, 0x0200, 9, wr_val)
#define rd_eagle_tsc_dfe_3_inv_p1()                             _eagle_tsc_pmd_rde_field_byte(0xd025, 7, 15, __ERR)
#define wr_eagle_tsc_dfe_3_inv_p1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd025, 0x0100, 8, wr_val)
#define rd_eagle_tsc_dfe_3_acc_clr()                            _eagle_tsc_pmd_rde_field_byte(0xd025, 15, 15, __ERR)
#define wr_eagle_tsc_dfe_3_acc_clr(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd025, 0x0001, 0, wr_val)
#define rd_eagle_tsc_dfe_3_pattern_bit_en()                     _eagle_tsc_pmd_rde_field_byte(0xd026, 2, 10, __ERR)
#define wr_eagle_tsc_dfe_3_pattern_bit_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd026, 0x3f00, 8, wr_val)
#define rd_eagle_tsc_dfe_3_pattern()                            _eagle_tsc_pmd_rde_field_byte(0xd026, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_3_pattern(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd026, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_4_en()                                 _eagle_tsc_pmd_rde_field_byte(0xd027, 0, 15, __ERR)
#define wr_eagle_tsc_dfe_4_en(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd027, 0x8000, 15, wr_val)
#define rd_eagle_tsc_dfe_4_err_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd027, 1, 14, __ERR)
#define wr_eagle_tsc_dfe_4_err_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd027, 0x6000, 13, wr_val)
#define rd_eagle_tsc_dfe_4_gradient_invert()                    _eagle_tsc_pmd_rde_field_byte(0xd027, 3, 15, __ERR)
#define wr_eagle_tsc_dfe_4_gradient_invert(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd027, 0x1000, 12, wr_val)
#define rd_eagle_tsc_dfe_4_err_gain()                           _eagle_tsc_pmd_rde_field_byte(0xd027, 4, 14, __ERR)
#define wr_eagle_tsc_dfe_4_err_gain(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd027, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_dfe_4_inv_m1()                             _eagle_tsc_pmd_rde_field_byte(0xd027, 6, 15, __ERR)
#define wr_eagle_tsc_dfe_4_inv_m1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd027, 0x0200, 9, wr_val)
#define rd_eagle_tsc_dfe_4_inv_p1()                             _eagle_tsc_pmd_rde_field_byte(0xd027, 7, 15, __ERR)
#define wr_eagle_tsc_dfe_4_inv_p1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd027, 0x0100, 8, wr_val)
#define rd_eagle_tsc_dfe_4_acc_clr()                            _eagle_tsc_pmd_rde_field_byte(0xd027, 15, 15, __ERR)
#define wr_eagle_tsc_dfe_4_acc_clr(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd027, 0x0001, 0, wr_val)
#define rd_eagle_tsc_dfe_4_pattern_bit_en()                     _eagle_tsc_pmd_rde_field_byte(0xd028, 2, 10, __ERR)
#define wr_eagle_tsc_dfe_4_pattern_bit_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd028, 0x3f00, 8, wr_val)
#define rd_eagle_tsc_dfe_4_pattern()                            _eagle_tsc_pmd_rde_field_byte(0xd028, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_4_pattern(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd028, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_5_en()                                 _eagle_tsc_pmd_rde_field_byte(0xd029, 0, 15, __ERR)
#define wr_eagle_tsc_dfe_5_en(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd029, 0x8000, 15, wr_val)
#define rd_eagle_tsc_dfe_5_err_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd029, 1, 14, __ERR)
#define wr_eagle_tsc_dfe_5_err_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd029, 0x6000, 13, wr_val)
#define rd_eagle_tsc_dfe_5_gradient_invert()                    _eagle_tsc_pmd_rde_field_byte(0xd029, 3, 15, __ERR)
#define wr_eagle_tsc_dfe_5_gradient_invert(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd029, 0x1000, 12, wr_val)
#define rd_eagle_tsc_dfe_5_err_gain()                           _eagle_tsc_pmd_rde_field_byte(0xd029, 4, 14, __ERR)
#define wr_eagle_tsc_dfe_5_err_gain(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd029, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_dfe_5_inv_m1()                             _eagle_tsc_pmd_rde_field_byte(0xd029, 6, 15, __ERR)
#define wr_eagle_tsc_dfe_5_inv_m1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd029, 0x0200, 9, wr_val)
#define rd_eagle_tsc_dfe_5_inv_p1()                             _eagle_tsc_pmd_rde_field_byte(0xd029, 7, 15, __ERR)
#define wr_eagle_tsc_dfe_5_inv_p1(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd029, 0x0100, 8, wr_val)
#define rd_eagle_tsc_dfe_5_acc_clr()                            _eagle_tsc_pmd_rde_field_byte(0xd029, 15, 15, __ERR)
#define wr_eagle_tsc_dfe_5_acc_clr(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd029, 0x0001, 0, wr_val)
#define rd_eagle_tsc_dfe_5_pattern_bit_en()                     _eagle_tsc_pmd_rde_field_byte(0xd02a, 2, 10, __ERR)
#define wr_eagle_tsc_dfe_5_pattern_bit_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd02a, 0x3f00, 8, wr_val)
#define rd_eagle_tsc_dfe_5_pattern()                            _eagle_tsc_pmd_rde_field_byte(0xd02a, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_5_pattern(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd02a, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_acc_hys_en()                           _eagle_tsc_pmd_rde_field_byte(0xd020, 0, 15, __ERR)
#define wr_eagle_tsc_dfe_acc_hys_en(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd020, 0x8000, 15, wr_val)
#define rd_eagle_tsc_dfe_allow_simult()                         _eagle_tsc_pmd_rde_field_byte(0xd020, 1, 15, __ERR)
#define wr_eagle_tsc_dfe_allow_simult(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd020, 0x4000, 14, wr_val)
#define rd_eagle_tsc_dfe_update_gain()                          _eagle_tsc_pmd_rde_field_byte(0xd020, 2, 15, __ERR)
#define wr_eagle_tsc_dfe_update_gain(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd020, 0x2000, 13, wr_val)
#define rd_eagle_tsc_dfe_vga_write_en()                         _eagle_tsc_pmd_rde_field_byte(0xd02b, 0, 15, __ERR)
#define wr_eagle_tsc_dfe_vga_write_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd02b, 0x8000, 15, wr_val)
#define rd_eagle_tsc_dfe_vga_write_tapsel()                     _eagle_tsc_pmd_rde_field_byte(0xd02b, 2, 11, __ERR)
#define wr_eagle_tsc_dfe_vga_write_tapsel(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd02b, 0x3e00, 9, wr_val)
#define rd_eagle_tsc_dfe_vga_write_val()                        _eagle_tsc_pmd_rde_field(0xd02b, 7, 7, __ERR)
#define wr_eagle_tsc_dfe_vga_write_val(wr_val)                  eagle_tsc_pmd_mwr_reg(0xd02b, 0x01ff, 0, wr_val)
#define rd_eagle_tsc_vga_en()                                   _eagle_tsc_pmd_rde_field_byte(0xd02c, 0, 15, __ERR)
#define wr_eagle_tsc_vga_en(wr_val)                             _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x8000, 15, wr_val)
#define rd_eagle_tsc_vga_err_sel()                              _eagle_tsc_pmd_rde_field_byte(0xd02c, 1, 14, __ERR)
#define wr_eagle_tsc_vga_err_sel(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x6000, 13, wr_val)
#define rd_eagle_tsc_vga_p1_gradient_invert()                   _eagle_tsc_pmd_rde_field_byte(0xd02c, 3, 15, __ERR)
#define wr_eagle_tsc_vga_p1_gradient_invert(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x1000, 12, wr_val)
#define rd_eagle_tsc_vga_err_gain()                             _eagle_tsc_pmd_rde_field_byte(0xd02c, 4, 14, __ERR)
#define wr_eagle_tsc_vga_err_gain(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_vga_inv_m1()                               _eagle_tsc_pmd_rde_field_byte(0xd02c, 6, 15, __ERR)
#define wr_eagle_tsc_vga_inv_m1(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x0200, 9, wr_val)
#define rd_eagle_tsc_vga_inv_p1()                               _eagle_tsc_pmd_rde_field_byte(0xd02c, 7, 15, __ERR)
#define wr_eagle_tsc_vga_inv_p1(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x0100, 8, wr_val)
#define rd_eagle_tsc_vga_update_gain()                          _eagle_tsc_pmd_rde_field_byte(0xd02c, 8, 14, __ERR)
#define wr_eagle_tsc_vga_update_gain(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x00c0, 6, wr_val)
#define rd_eagle_tsc_vga_tablemap_disable()                     _eagle_tsc_pmd_rde_field_byte(0xd02c, 13, 15, __ERR)
#define wr_eagle_tsc_vga_tablemap_disable(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x0004, 2, wr_val)
#define rd_eagle_tsc_vga_acc_hys_en()                           _eagle_tsc_pmd_rde_field_byte(0xd02c, 14, 15, __ERR)
#define wr_eagle_tsc_vga_acc_hys_en(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x0002, 1, wr_val)
#define rd_eagle_tsc_vga_p1_acc_clr()                           _eagle_tsc_pmd_rde_field_byte(0xd02c, 15, 15, __ERR)
#define wr_eagle_tsc_vga_p1_acc_clr(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd02c, 0x0001, 0, wr_val)
#define rd_eagle_tsc_p1_eyediag_en()                            _eagle_tsc_pmd_rde_field_byte(0xd02d, 0, 15, __ERR)
#define wr_eagle_tsc_p1_eyediag_en(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd02d, 0x8000, 15, wr_val)
#define rd_eagle_tsc_vga_pattern_bit_en()                       _eagle_tsc_pmd_rde_field_byte(0xd02d, 8, 12, __ERR)
#define wr_eagle_tsc_vga_pattern_bit_en(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd02d, 0x00f0, 4, wr_val)
#define rd_eagle_tsc_vga_pattern()                              _eagle_tsc_pmd_rde_field_byte(0xd02d, 12, 12, __ERR)
#define wr_eagle_tsc_vga_pattern(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd02d, 0x000f, 0, wr_val)
#define rd_eagle_tsc_p1_off_3levelq_en()                        _eagle_tsc_pmd_rde_field_byte(0xd02e, 7, 15, __ERR)
#define wr_eagle_tsc_p1_off_3levelq_en(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd02e, 0x0100, 8, wr_val)
#define rd_eagle_tsc_p1_offset_en()                             _eagle_tsc_pmd_rde_field_byte(0xd02e, 8, 15, __ERR)
#define wr_eagle_tsc_p1_offset_en(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd02e, 0x0080, 7, wr_val)
#define rd_eagle_tsc_p1_offset()                                _eagle_tsc_pmd_rde_field_signed_byte(0xd02e, 9, 9, __ERR)
#define wr_eagle_tsc_p1_offset(wr_val)                          _eagle_tsc_pmd_mwr_reg_byte(0xd02e, 0x007f, 0, wr_val)
#define rd_eagle_tsc_trnsum_en()                                _eagle_tsc_pmd_rde_field_byte(0xd030, 0, 15, __ERR)
#define wr_eagle_tsc_trnsum_en(wr_val)                          _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x8000, 15, wr_val)
#define rd_eagle_tsc_trnsum_err_sel()                           _eagle_tsc_pmd_rde_field_byte(0xd030, 1, 13, __ERR)
#define wr_eagle_tsc_trnsum_err_sel(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x7000, 12, wr_val)
#define rd_eagle_tsc_trnsum_random_tapsel_disable()             _eagle_tsc_pmd_rde_field_byte(0xd030, 4, 15, __ERR)
#define wr_eagle_tsc_trnsum_random_tapsel_disable(wr_val)       _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x0800, 11, wr_val)
#define rd_eagle_tsc_trnsum_inv_pattern_en()                    _eagle_tsc_pmd_rde_field_byte(0xd030, 5, 15, __ERR)
#define wr_eagle_tsc_trnsum_inv_pattern_en(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x0400, 10, wr_val)
#define rd_eagle_tsc_trnsum_pattern_full_check_off()            _eagle_tsc_pmd_rde_field_byte(0xd030, 6, 15, __ERR)
#define wr_eagle_tsc_trnsum_pattern_full_check_off(wr_val)      _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x0200, 9, wr_val)
#define rd_eagle_tsc_trnsum_gain()                              _eagle_tsc_pmd_rde_field_byte(0xd030, 8, 14, __ERR)
#define wr_eagle_tsc_trnsum_gain(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x00c0, 6, wr_val)
#define rd_eagle_tsc_trnsum_eye_closure_en()                    _eagle_tsc_pmd_rde_field_byte(0xd030, 10, 15, __ERR)
#define wr_eagle_tsc_trnsum_eye_closure_en(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x0020, 5, wr_val)
#define rd_eagle_tsc_cdr_qphase_mult_en()                       _eagle_tsc_pmd_rde_field_byte(0xd030, 11, 15, __ERR)
#define wr_eagle_tsc_cdr_qphase_mult_en(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x0010, 4, wr_val)
#define rd_eagle_tsc_trnsum_tap_range_sel()                     _eagle_tsc_pmd_rde_field_byte(0xd030, 12, 14, __ERR)
#define wr_eagle_tsc_trnsum_tap_range_sel(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd030, 0x000c, 2, wr_val)
#define rd_eagle_tsc_trnsum_pattern()                           _eagle_tsc_pmd_rde_field_byte(0xd031, 0, 8, __ERR)
#define wr_eagle_tsc_trnsum_pattern(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd031, 0xff00, 8, wr_val)
#define rd_eagle_tsc_trnsum_pattern_bit_en()                    _eagle_tsc_pmd_rde_field_byte(0xd031, 8, 8, __ERR)
#define wr_eagle_tsc_trnsum_pattern_bit_en(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd031, 0x00ff, 0, wr_val)
#define rd_eagle_tsc_trnsum_tap_en()                            _eagle_tsc_pmd_rde_field_byte(0xd032, 0, 8, __ERR)
#define wr_eagle_tsc_trnsum_tap_en(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd032, 0xff00, 8, wr_val)
#define rd_eagle_tsc_trnsum_tap_sign()                          _eagle_tsc_pmd_rde_field_byte(0xd032, 8, 8, __ERR)
#define wr_eagle_tsc_trnsum_tap_sign(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd032, 0x00ff, 0, wr_val)
#define rd_eagle_tsc_tdr_cycle_bin()                            _eagle_tsc_pmd_rde_field_byte(0xd033, 0, 12, __ERR)
#define wr_eagle_tsc_tdr_cycle_bin(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd033, 0xf000, 12, wr_val)
#define rd_eagle_tsc_tdr_cycle_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd033, 4, 12, __ERR)
#define wr_eagle_tsc_tdr_cycle_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd033, 0x0f00, 8, wr_val)
#define rd_eagle_tsc_tdr_trnsum_en()                            _eagle_tsc_pmd_rde_field_byte(0xd033, 8, 15, __ERR)
#define wr_eagle_tsc_tdr_trnsum_en(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd033, 0x0080, 7, wr_val)
#define rd_eagle_tsc_tdr_bit_sel()                              _eagle_tsc_pmd_rde_field_byte(0xd033, 9, 11, __ERR)
#define wr_eagle_tsc_tdr_bit_sel(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd033, 0x007c, 2, wr_val)
#define rd_eagle_tsc_trnsum_unsigned_flip()                     _eagle_tsc_pmd_rde_field_byte(0xd033, 14, 15, __ERR)
#define wr_eagle_tsc_trnsum_unsigned_flip(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd033, 0x0002, 1, wr_val)
#define rd_eagle_tsc_trnsum_unsigned_corr()                     _eagle_tsc_pmd_rde_field_byte(0xd033, 15, 15, __ERR)
#define wr_eagle_tsc_trnsum_unsigned_corr(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd033, 0x0001, 0, wr_val)
#define rd_eagle_tsc_trnsum_e_high()                            _eagle_tsc_pmd_rde_field_signed(0xd034, 0, 0, __ERR)
#define rd_eagle_tsc_trnsum_e_low()                             _eagle_tsc_pmd_rde_field_byte(0xd035, 8, 8, __ERR)
#define rd_eagle_tsc_trnsum_o_high()                            _eagle_tsc_pmd_rde_field_signed(0xd036, 0, 0, __ERR)
#define rd_eagle_tsc_trnsum_o_low()                             _eagle_tsc_pmd_rde_field_byte(0xd037, 8, 8, __ERR)
#define rd_eagle_tsc_trnsum_high()                              _eagle_tsc_pmd_rde_field_signed(0xd038, 0, 0, __ERR)
#define rd_eagle_tsc_trnsum_low()                               _eagle_tsc_pmd_rde_field(0xd039, 6, 6, __ERR)
#define rd_eagle_tsc_p1_eyediag_bin()                           _eagle_tsc_pmd_rde_field_signed_byte(0xd03a, 2, 10, __ERR)
#define rd_eagle_tsc_vga_bin()                                  _eagle_tsc_pmd_rde_field_byte(0xd03a, 10, 10, __ERR)
#define rd_eagle_tsc_dfe_1_wants_negative()                     _eagle_tsc_pmd_rde_field_byte(0xd03b, 0, 15, __ERR)
#define rd_eagle_tsc_dfe_1_e()                                  _eagle_tsc_pmd_rde_field_byte(0xd03b, 2, 13, __ERR)
#define rd_eagle_tsc_dfe_1_o()                                  _eagle_tsc_pmd_rde_field_byte(0xd03b, 5, 13, __ERR)
#define rd_eagle_tsc_dfe_1_cmn()                                _eagle_tsc_pmd_rde_field_byte(0xd03b, 10, 10, __ERR)
#define rd_eagle_tsc_dfe_2_e()                                  _eagle_tsc_pmd_rde_field_byte(0xd03c, 2, 13, __ERR)
#define rd_eagle_tsc_dfe_2_o()                                  _eagle_tsc_pmd_rde_field_byte(0xd03c, 5, 13, __ERR)
#define rd_eagle_tsc_dfe_2_se()                                 _eagle_tsc_pmd_rde_field_byte(0xd03c, 9, 15, __ERR)
#define rd_eagle_tsc_dfe_2_so()                                 _eagle_tsc_pmd_rde_field_byte(0xd03c, 10, 15, __ERR)
#define rd_eagle_tsc_dfe_2_cmn()                                _eagle_tsc_pmd_rde_field_byte(0xd03c, 11, 11, __ERR)
#define rd_eagle_tsc_dfe_5_cmn()                                _eagle_tsc_pmd_rde_field_signed_byte(0xd03d, 0, 11, __ERR)
#define rd_eagle_tsc_dfe_4_cmn()                                _eagle_tsc_pmd_rde_field_signed_byte(0xd03d, 5, 11, __ERR)
#define rd_eagle_tsc_dfe_3_cmn()                                _eagle_tsc_pmd_rde_field_signed_byte(0xd03d, 10, 10, __ERR)
#define rd_eagle_tsc_vga3_ctrl_bin()                            _eagle_tsc_pmd_rde_field_byte(0xd03e, 4, 12, __ERR)
#define rd_eagle_tsc_vga_ctrl_bin()                             _eagle_tsc_pmd_rde_field_byte(0xd03e, 11, 11, __ERR)
#define rd_eagle_tsc_offset_fastacq()                           _eagle_tsc_pmd_rde_field_byte(0xd040, 6, 15, __ERR)
#define wr_eagle_tsc_offset_fastacq(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0200, 9, wr_val)
#define rd_eagle_tsc_en_dfe_clk()                               _eagle_tsc_pmd_rde_field_byte(0xd040, 7, 15, __ERR)
#define wr_eagle_tsc_en_dfe_clk(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0100, 8, wr_val)
#define rd_eagle_tsc_pf_hiz()                                   _eagle_tsc_pmd_rde_field_byte(0xd040, 8, 15, __ERR)
#define wr_eagle_tsc_pf_hiz(wr_val)                             _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0080, 7, wr_val)
#define rd_eagle_tsc_m1_thresh_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd040, 9, 14, __ERR)
#define wr_eagle_tsc_m1_thresh_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0060, 5, wr_val)
#define rd_eagle_tsc_m1_thresh_zero()                           _eagle_tsc_pmd_rde_field_byte(0xd040, 11, 15, __ERR)
#define wr_eagle_tsc_m1_thresh_zero(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0010, 4, wr_val)
#define rd_eagle_tsc_p1_thresh_sel()                            _eagle_tsc_pmd_rde_field_byte(0xd040, 12, 15, __ERR)
#define wr_eagle_tsc_p1_thresh_sel(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0008, 3, wr_val)
#define rd_eagle_tsc_en_hgain()                                 _eagle_tsc_pmd_rde_field_byte(0xd040, 13, 15, __ERR)
#define wr_eagle_tsc_en_hgain(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0004, 2, wr_val)
#define rd_eagle_tsc_offset_pd()                                _eagle_tsc_pmd_rde_field_byte(0xd040, 14, 15, __ERR)
#define wr_eagle_tsc_offset_pd(wr_val)                          _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0002, 1, wr_val)
#define rd_eagle_tsc_pd_ch_p1()                                 _eagle_tsc_pmd_rde_field_byte(0xd040, 15, 15, __ERR)
#define wr_eagle_tsc_pd_ch_p1(wr_val)                           _eagle_tsc_pmd_mwr_reg_byte(0xd040, 0x0001, 0, wr_val)
#define rd_eagle_tsc_pf_ctrl()                                  _eagle_tsc_pmd_rde_field_byte(0xd041, 12, 12, __ERR)
#define wr_eagle_tsc_pf_ctrl(wr_val)                            _eagle_tsc_pmd_mwr_reg_byte(0xd041, 0x000f, 0, wr_val)
#define rd_eagle_tsc_pf2_lowp_ctrl()                            _eagle_tsc_pmd_rde_field_byte(0xd042, 13, 13, __ERR)
#define wr_eagle_tsc_pf2_lowp_ctrl(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd042, 0x0007, 0, wr_val)
#define rd_eagle_tsc_dfe_offset_adj_data_odd()                  _eagle_tsc_pmd_rde_field_signed_byte(0xd043, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_offset_adj_data_odd(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd043, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_offset_adj_data_even()                 _eagle_tsc_pmd_rde_field_signed_byte(0xd044, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_offset_adj_data_even(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd044, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_offset_adj_p1_odd()                    _eagle_tsc_pmd_rde_field_signed_byte(0xd045, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_offset_adj_p1_odd(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd045, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_offset_adj_p1_even()                   _eagle_tsc_pmd_rde_field_signed_byte(0xd046, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_offset_adj_p1_even(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd046, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_offset_adj_m1_odd()                    _eagle_tsc_pmd_rde_field_signed_byte(0xd047, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_offset_adj_m1_odd(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd047, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dfe_offset_adj_m1_even()                   _eagle_tsc_pmd_rde_field_signed_byte(0xd048, 10, 10, __ERR)
#define wr_eagle_tsc_dfe_offset_adj_m1_even(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd048, 0x003f, 0, wr_val)
#define rd_eagle_tsc_dc_offset()                                _eagle_tsc_pmd_rde_field_signed_byte(0xd049, 9, 9, __ERR)
#define wr_eagle_tsc_dc_offset(wr_val)                          _eagle_tsc_pmd_mwr_reg_byte(0xd049, 0x007f, 0, wr_val)
#define rdc_eagle_tsc_mdio_blk_addr()                           _eagle_tsc_pmd_rde_field(0xffdf, 1, 5, __ERR)
#define wrc_eagle_tsc_mdio_blk_addr(wr_val)                     eagle_tsc_pmd_mwr_reg(0xffdf, 0x7ff0, 4, wr_val)
#define rdc_eagle_tsc_mdio_function()                           _eagle_tsc_pmd_rde_field_byte(0x000d, 0, 14, __ERR)
#define wrc_eagle_tsc_mdio_function(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0x000d, 0xc000, 14, wr_val)
#define rdc_eagle_tsc_mdio_devad()                              _eagle_tsc_pmd_rde_field_byte(0x000d, 11, 11, __ERR)
#define wrc_eagle_tsc_mdio_devad(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0x000d, 0x001f, 0, wr_val)
#define rdc_eagle_tsc_mdio_addr_data()                          _eagle_tsc_pmd_rde_reg(0x000e, __ERR)
#define wrc_eagle_tsc_mdio_addr_data(wr_val)                    eagle_tsc_pmd_wr_reg(0x000e, wr_val)
#define rdc_eagle_tsc_mdio_maskdata()                           _eagle_tsc_pmd_rde_reg(0xffdb, __ERR)
#define wrc_eagle_tsc_mdio_maskdata(wr_val)                     eagle_tsc_pmd_wr_reg(0xffdb, wr_val)
#define rdc_eagle_tsc_mdio_brcst_port_addr()                    _eagle_tsc_pmd_rde_field_byte(0xffdc, 11, 11, __ERR)
#define wrc_eagle_tsc_mdio_brcst_port_addr(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xffdc, 0x001f, 0, wr_val)
#define rdc_eagle_tsc_mdio_multi_prts_en()                      _eagle_tsc_pmd_rde_field_byte(0xffdd, 0, 15, __ERR)
#define wrc_eagle_tsc_mdio_multi_prts_en(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_mdio_multi_mmds_en()                      _eagle_tsc_pmd_rde_field_byte(0xffdd, 1, 15, __ERR)
#define wrc_eagle_tsc_mdio_multi_mmds_en(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_mdio_dev_pcs_en()                         _eagle_tsc_pmd_rde_field_byte(0xffdd, 9, 15, __ERR)
#define wrc_eagle_tsc_mdio_dev_pcs_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_mdio_dev_dte_en()                         _eagle_tsc_pmd_rde_field_byte(0xffdd, 10, 15, __ERR)
#define wrc_eagle_tsc_mdio_dev_dte_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_mdio_dev_phy_en()                         _eagle_tsc_pmd_rde_field_byte(0xffdd, 11, 15, __ERR)
#define wrc_eagle_tsc_mdio_dev_phy_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_mdio_dev_an_en()                          _eagle_tsc_pmd_rde_field_byte(0xffdd, 12, 15, __ERR)
#define wrc_eagle_tsc_mdio_dev_an_en(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_mdio_dev_pmd_en()                         _eagle_tsc_pmd_rde_field_byte(0xffdd, 13, 15, __ERR)
#define wrc_eagle_tsc_mdio_dev_pmd_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_mdio_dev_cl22_en()                        _eagle_tsc_pmd_rde_field_byte(0xffdd, 15, 15, __ERR)
#define wrc_eagle_tsc_mdio_dev_cl22_en(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xffdd, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_mdio_aer()                                _eagle_tsc_pmd_rde_reg(0xffde, __ERR)
#define wrc_eagle_tsc_mdio_aer(wr_val)                          eagle_tsc_pmd_wr_reg(0xffde, wr_val)
#define rdc_eagle_tsc_micro_ram_count()                         _eagle_tsc_pmd_rde_reg(0xd200, __ERR)
#define wrc_eagle_tsc_micro_ram_count(wr_val)                   eagle_tsc_pmd_wr_reg(0xd200, wr_val)
#define rdc_eagle_tsc_micro_ram_address()                       _eagle_tsc_pmd_rde_reg(0xd201, __ERR)
#define wrc_eagle_tsc_micro_ram_address(wr_val)                 eagle_tsc_pmd_wr_reg(0xd201, wr_val)
#define rdc_eagle_tsc_micro_init_cmd()                          _eagle_tsc_pmd_rde_field_byte(0xd202, 0, 15, __ERR)
#define wrc_eagle_tsc_micro_init_cmd(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_micro_pmi_hp_ack_frc_val()                _eagle_tsc_pmd_rde_field_byte(0xd202, 1, 15, __ERR)
#define wrc_eagle_tsc_micro_pmi_hp_ack_frc_val(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_micro_pmi_hp_ack_frc()                    _eagle_tsc_pmd_rde_field_byte(0xd202, 2, 15, __ERR)
#define wrc_eagle_tsc_micro_pmi_hp_ack_frc(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x2000, 13, wr_val)
#define rdc_eagle_tsc_micro_mdio_prog_ram_cs_frc_val()          _eagle_tsc_pmd_rde_field_byte(0xd202, 3, 15, __ERR)
#define wrc_eagle_tsc_micro_mdio_prog_ram_cs_frc_val(wr_val)    _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x1000, 12, wr_val)
#define rdc_eagle_tsc_micro_mdio_prog_ram_cs_frc()              _eagle_tsc_pmd_rde_field_byte(0xd202, 4, 15, __ERR)
#define wrc_eagle_tsc_micro_mdio_prog_ram_cs_frc(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_micro_mdio_autowakeup()                   _eagle_tsc_pmd_rde_field_byte(0xd202, 5, 15, __ERR)
#define wrc_eagle_tsc_micro_mdio_autowakeup(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_micro_byte_mode()                         _eagle_tsc_pmd_rde_field_byte(0xd202, 6, 15, __ERR)
#define wrc_eagle_tsc_micro_byte_mode(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0200, 9, wr_val)
#define rdc_eagle_tsc_micro_mdio_ram_access_mode()              _eagle_tsc_pmd_rde_field_byte(0xd202, 7, 14, __ERR)
#define wrc_eagle_tsc_micro_mdio_ram_access_mode(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0180, 7, wr_val)
#define rdc_eagle_tsc_micro_mdio_ram_read_autoinc_en()          _eagle_tsc_pmd_rde_field_byte(0xd202, 9, 15, __ERR)
#define wrc_eagle_tsc_micro_mdio_ram_read_autoinc_en(wr_val)    _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_micro_mdio_dw8051_reset_n()               _eagle_tsc_pmd_rde_field_byte(0xd202, 11, 15, __ERR)
#define wrc_eagle_tsc_micro_mdio_dw8051_reset_n(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_micro_write()                             _eagle_tsc_pmd_rde_field_byte(0xd202, 12, 15, __ERR)
#define wrc_eagle_tsc_micro_write(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_micro_read()                              _eagle_tsc_pmd_rde_field_byte(0xd202, 13, 15, __ERR)
#define wrc_eagle_tsc_micro_read(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_micro_stop()                              _eagle_tsc_pmd_rde_field_byte(0xd202, 14, 15, __ERR)
#define wrc_eagle_tsc_micro_stop(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_micro_run()                               _eagle_tsc_pmd_rde_field_byte(0xd202, 15, 15, __ERR)
#define wrc_eagle_tsc_micro_run(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd202, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_micro_ram_wrdata()                        _eagle_tsc_pmd_rde_reg(0xd203, __ERR)
#define wrc_eagle_tsc_micro_ram_wrdata(wr_val)                  eagle_tsc_pmd_wr_reg(0xd203, wr_val)
#define rdc_eagle_tsc_micro_ram_rddata()                        _eagle_tsc_pmd_rde_reg(0xd204, __ERR)
#define rdc_eagle_tsc_micro_init_done()                         _eagle_tsc_pmd_rde_field_byte(0xd205, 0, 15, __ERR)
#define rdc_eagle_tsc_micro_fsm()                               _eagle_tsc_pmd_rde_field_byte(0xd205, 10, 12, __ERR)
#define rdc_eagle_tsc_micro_err1()                              _eagle_tsc_pmd_rde_field_byte(0xd205, 14, 15, __ERR)
#define rdc_eagle_tsc_micro_err0()                              _eagle_tsc_pmd_rde_field_byte(0xd205, 15, 15, __ERR)
#define rdc_eagle_tsc_micro_status_muxed()                      _eagle_tsc_pmd_rde_reg(0xd206, __ERR)
#define rdc_eagle_tsc_micro_mdio_uc_mailbox_msw()               _eagle_tsc_pmd_rde_reg(0xd207, __ERR)
#define wrc_eagle_tsc_micro_mdio_uc_mailbox_msw(wr_val)         eagle_tsc_pmd_wr_reg(0xd207, wr_val)
#define rdc_eagle_tsc_micro_mdio_uc_mailbox_lsw()               _eagle_tsc_pmd_rde_reg(0xd208, __ERR)
#define wrc_eagle_tsc_micro_mdio_uc_mailbox_lsw(wr_val)         eagle_tsc_pmd_wr_reg(0xd208, wr_val)
#define rdc_eagle_tsc_micro_uc_mdio_mailbox_msw()               _eagle_tsc_pmd_rde_reg(0xd20b, __ERR)
#define rdc_eagle_tsc_micro_uc_mdio_mailbox_lsw()               _eagle_tsc_pmd_rde_reg(0xd209, __ERR)
#define rdc_eagle_tsc_micro_srst_dw8051_to_pmi()                _eagle_tsc_pmd_rde_field_byte(0xd20a, 0, 15, __ERR)
#define wrc_eagle_tsc_micro_srst_dw8051_to_pmi(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd20a, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_micro_srst_mdio_program_access()          _eagle_tsc_pmd_rde_field_byte(0xd20a, 1, 15, __ERR)
#define wrc_eagle_tsc_micro_srst_mdio_program_access(wr_val)    _eagle_tsc_pmd_mwr_reg_byte(0xd20a, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_micro_srst_mdio_load_program_ram()        _eagle_tsc_pmd_rde_field_byte(0xd20a, 2, 15, __ERR)
#define wrc_eagle_tsc_micro_srst_mdio_load_program_ram(wr_val)  _eagle_tsc_pmd_mwr_reg_byte(0xd20a, 0x2000, 13, wr_val)
#define rdc_eagle_tsc_micro_zero_rom_dataout()                  _eagle_tsc_pmd_rde_field_byte(0xd20a, 3, 15, __ERR)
#define wrc_eagle_tsc_micro_zero_rom_dataout(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd20a, 0x1000, 12, wr_val)
#define rdc_eagle_tsc_micro_ram_clk_invert()                    _eagle_tsc_pmd_rde_field_byte(0xd20a, 4, 15, __ERR)
#define wrc_eagle_tsc_micro_ram_clk_invert(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd20a, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_micro_srst_mdio_dataram_access()          _eagle_tsc_pmd_rde_field_byte(0xd20a, 5, 15, __ERR)
#define wrc_eagle_tsc_micro_srst_mdio_dataram_access(wr_val)    _eagle_tsc_pmd_mwr_reg_byte(0xd20a, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_micro_pmi_ack_timeout_val()               _eagle_tsc_pmd_rde_field_byte(0xd20a, 12, 12, __ERR)
#define wrc_eagle_tsc_micro_pmi_ack_timeout_val(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd20a, 0x000f, 0, wr_val)
#define rdc_eagle_tsc_micro_gen_status_sel()                    _eagle_tsc_pmd_rde_field_byte(0xd20c, 0, 13, __ERR)
#define wrc_eagle_tsc_micro_gen_status_sel(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd20c, 0xe000, 13, wr_val)
#define rdc_eagle_tsc_micro_disable_ecc()                       _eagle_tsc_pmd_rde_field_byte(0xd20c, 3, 15, __ERR)
#define wrc_eagle_tsc_micro_disable_ecc(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd20c, 0x1000, 12, wr_val)
#define rdc_eagle_tsc_micro_inrush_current_frc_val()            _eagle_tsc_pmd_rde_field_byte(0xd20c, 4, 15, __ERR)
#define wrc_eagle_tsc_micro_inrush_current_frc_val(wr_val)      _eagle_tsc_pmd_mwr_reg_byte(0xd20c, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_micro_inrush_current_frc()                _eagle_tsc_pmd_rde_field_byte(0xd20c, 5, 15, __ERR)
#define wrc_eagle_tsc_micro_inrush_current_frc(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd20c, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_micro_pram_if_rstb()                      _eagle_tsc_pmd_rde_field_byte(0xd20c, 13, 15, __ERR)
#define wrc_eagle_tsc_micro_pram_if_rstb(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd20c, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_micro_pram_if_flop_bypass()               _eagle_tsc_pmd_rde_field_byte(0xd20c, 14, 15, __ERR)
#define wrc_eagle_tsc_micro_pram_if_flop_bypass(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd20c, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_micro_pram_if_en()                        _eagle_tsc_pmd_rde_field_byte(0xd20c, 15, 15, __ERR)
#define wrc_eagle_tsc_micro_pram_if_en(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd20c, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_micro_system_reset_n()                    _eagle_tsc_pmd_rde_field_byte(0xd20d, 14, 15, __ERR)
#define wrc_eagle_tsc_micro_system_reset_n(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd20d, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_micro_system_clk_en()                     _eagle_tsc_pmd_rde_field_byte(0xd20d, 15, 15, __ERR)
#define wrc_eagle_tsc_micro_system_clk_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd20d, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_micro_tempature_data()                    _eagle_tsc_pmd_rde_reg(0xd20e, __ERR)
#define rdc_eagle_tsc_micro_program_ram_tm()                    _eagle_tsc_pmd_rde_field(0xd210, 2, 2, __ERR)
#define wrc_eagle_tsc_micro_program_ram_tm(wr_val)              eagle_tsc_pmd_mwr_reg(0xd210, 0x3fff, 0, wr_val)
#define rdc_eagle_tsc_micro_dataram_tm()                        _eagle_tsc_pmd_rde_field(0xd214, 6, 6, __ERR)
#define wrc_eagle_tsc_micro_dataram_tm(wr_val)                  eagle_tsc_pmd_mwr_reg(0xd214, 0x03ff, 0, wr_val)
#define rdc_eagle_tsc_micro_iram_tm()                           _eagle_tsc_pmd_rde_field(0xd218, 6, 6, __ERR)
#define wrc_eagle_tsc_micro_iram_tm(wr_val)                     eagle_tsc_pmd_mwr_reg(0xd218, 0x03ff, 0, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_0()                          _eagle_tsc_pmd_rde_reg(0xd100, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_0(wr_val)                    eagle_tsc_pmd_wr_reg(0xd100, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_1()                          _eagle_tsc_pmd_rde_reg(0xd101, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_1(wr_val)                    eagle_tsc_pmd_wr_reg(0xd101, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_2()                          _eagle_tsc_pmd_rde_reg(0xd102, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_2(wr_val)                    eagle_tsc_pmd_wr_reg(0xd102, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_3()                          _eagle_tsc_pmd_rde_reg(0xd103, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_3(wr_val)                    eagle_tsc_pmd_wr_reg(0xd103, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_4()                          _eagle_tsc_pmd_rde_reg(0xd104, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_4(wr_val)                    eagle_tsc_pmd_wr_reg(0xd104, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_5()                          _eagle_tsc_pmd_rde_reg(0xd105, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_5(wr_val)                    eagle_tsc_pmd_wr_reg(0xd105, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_6()                          _eagle_tsc_pmd_rde_reg(0xd106, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_6(wr_val)                    eagle_tsc_pmd_wr_reg(0xd106, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_7()                          _eagle_tsc_pmd_rde_reg(0xd107, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_7(wr_val)                    eagle_tsc_pmd_wr_reg(0xd107, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_8()                          _eagle_tsc_pmd_rde_reg(0xd108, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_8(wr_val)                    eagle_tsc_pmd_wr_reg(0xd108, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_9()                          _eagle_tsc_pmd_rde_reg(0xd109, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_9(wr_val)                    eagle_tsc_pmd_wr_reg(0xd109, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_10()                         _eagle_tsc_pmd_rde_reg(0xd10a, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_10(wr_val)                   eagle_tsc_pmd_wr_reg(0xd10a, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_11()                         _eagle_tsc_pmd_rde_reg(0xd10b, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_11(wr_val)                   eagle_tsc_pmd_wr_reg(0xd10b, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_12()                         _eagle_tsc_pmd_rde_reg(0xd10c, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_12(wr_val)                   eagle_tsc_pmd_wr_reg(0xd10c, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_13()                         _eagle_tsc_pmd_rde_reg(0xd10d, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_13(wr_val)                   eagle_tsc_pmd_wr_reg(0xd10d, wr_val)
#define rdc_eagle_tsc_patt_gen_seq_14()                         _eagle_tsc_pmd_rde_reg(0xd10e, __ERR)
#define wrc_eagle_tsc_patt_gen_seq_14(wr_val)                   eagle_tsc_pmd_wr_reg(0xd10e, wr_val)
#define rdc_eagle_tsc_refclk_divcnt_sel()                       _eagle_tsc_pmd_rde_field_byte(0xd126, 13, 13, __ERR)
#define wrc_eagle_tsc_refclk_divcnt_sel(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd126, 0x0007, 0, wr_val)
#define rdc_eagle_tsc_rescal_in()                               _eagle_tsc_pmd_rde_field_byte(0xd129, 4, 12, __ERR)
#define rdc_eagle_tsc_cap_select()                              _eagle_tsc_pmd_rde_field_byte(0xd129, 8, 8, __ERR)
#define rdc_eagle_tsc_dbg_pll_state_one_hot()                   _eagle_tsc_pmd_rde_field_byte(0xd12a, 0, 8, __ERR)
#define rdc_eagle_tsc_dbg_cap_state_one_hot()                   _eagle_tsc_pmd_rde_field_byte(0xd12a, 8, 11, __ERR)
#define rdc_eagle_tsc_dbg_fdbck()                               _eagle_tsc_pmd_rde_field_byte(0xd12a, 13, 15, __ERR)
#define rdc_eagle_tsc_dbg_slowdn_change()                       _eagle_tsc_pmd_rde_field_byte(0xd12a, 14, 15, __ERR)
#define rdc_eagle_tsc_dbg_slowdn()                              _eagle_tsc_pmd_rde_field_byte(0xd12a, 15, 15, __ERR)
#define rdc_eagle_tsc_refclk_divcnt()                           _eagle_tsc_pmd_rde_field(0xd125, 2, 2, __ERR)
#define wrc_eagle_tsc_refclk_divcnt(wr_val)                     eagle_tsc_pmd_mwr_reg(0xd125, 0x3fff, 0, wr_val)
#define rdc_eagle_tsc_pll_seq_start()                           _eagle_tsc_pmd_rde_field_byte(0xd124, 0, 15, __ERR)
#define wrc_eagle_tsc_pll_seq_start(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x8000, 15, wr_val)
#define rdc_eagle_tsc_vco_done_en()                             _eagle_tsc_pmd_rde_field_byte(0xd124, 1, 15, __ERR)
#define wrc_eagle_tsc_vco_done_en(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x4000, 14, wr_val)
#define rdc_eagle_tsc_freq_det_retry_en()                       _eagle_tsc_pmd_rde_field_byte(0xd124, 2, 15, __ERR)
#define wrc_eagle_tsc_freq_det_retry_en(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x2000, 13, wr_val)
#define rdc_eagle_tsc_freq_det_restart_en()                     _eagle_tsc_pmd_rde_field_byte(0xd124, 3, 15, __ERR)
#define wrc_eagle_tsc_freq_det_restart_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x1000, 12, wr_val)
#define rdc_eagle_tsc_freq_monitor_en()                         _eagle_tsc_pmd_rde_field_byte(0xd124, 4, 15, __ERR)
#define wrc_eagle_tsc_freq_monitor_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0800, 11, wr_val)
#define rdc_eagle_tsc_slowdn_xor()                              _eagle_tsc_pmd_rde_field_byte(0xd124, 5, 15, __ERR)
#define wrc_eagle_tsc_slowdn_xor(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0400, 10, wr_val)
#define rdc_eagle_tsc_vco_rst_en()                              _eagle_tsc_pmd_rde_field_byte(0xd124, 6, 15, __ERR)
#define wrc_eagle_tsc_vco_rst_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0200, 9, wr_val)
#define rdc_eagle_tsc_pll_force_fdone_en()                      _eagle_tsc_pmd_rde_field_byte(0xd124, 7, 15, __ERR)
#define wrc_eagle_tsc_pll_force_fdone_en(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0100, 8, wr_val)
#define rdc_eagle_tsc_pll_force_fdone()                         _eagle_tsc_pmd_rde_field_byte(0xd124, 8, 15, __ERR)
#define wrc_eagle_tsc_pll_force_fdone(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_pll_force_fpass()                         _eagle_tsc_pmd_rde_field_byte(0xd124, 9, 15, __ERR)
#define wrc_eagle_tsc_pll_force_fpass(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_pll_force_cap_done_en()                   _eagle_tsc_pmd_rde_field_byte(0xd124, 10, 15, __ERR)
#define wrc_eagle_tsc_pll_force_cap_done_en(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_pll_force_cap_done()                      _eagle_tsc_pmd_rde_field_byte(0xd124, 11, 15, __ERR)
#define wrc_eagle_tsc_pll_force_cap_done(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_pll_force_cap_pass_en()                   _eagle_tsc_pmd_rde_field_byte(0xd124, 12, 15, __ERR)
#define wrc_eagle_tsc_pll_force_cap_pass_en(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_pll_force_cap_pass()                      _eagle_tsc_pmd_rde_field_byte(0xd124, 13, 15, __ERR)
#define wrc_eagle_tsc_pll_force_cap_pass(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_pll_lock_frc()                            _eagle_tsc_pmd_rde_field_byte(0xd124, 14, 15, __ERR)
#define wrc_eagle_tsc_pll_lock_frc(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_pll_lock_frc_val()                        _eagle_tsc_pmd_rde_field_byte(0xd124, 15, 15, __ERR)
#define wrc_eagle_tsc_pll_lock_frc_val(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd124, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_rescal_frc()                              _eagle_tsc_pmd_rde_field_byte(0xd127, 7, 15, __ERR)
#define wrc_eagle_tsc_rescal_frc(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd127, 0x0100, 8, wr_val)
#define rdc_eagle_tsc_rescal_frc_val()                          _eagle_tsc_pmd_rde_field_byte(0xd127, 8, 12, __ERR)
#define wrc_eagle_tsc_rescal_frc_val(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd127, 0x00f0, 4, wr_val)
#define rdc_eagle_tsc_pll_mode()                                _eagle_tsc_pmd_rde_field_byte(0xd127, 12, 12, __ERR)
#define wrc_eagle_tsc_pll_mode(wr_val)                          _eagle_tsc_pmd_mwr_reg_byte(0xd127, 0x000f, 0, wr_val)
#define rdc_eagle_tsc_cap_select_m()                            _eagle_tsc_pmd_rde_field_byte(0xd123, 0, 8, __ERR)
#define wrc_eagle_tsc_cap_select_m(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0xff00, 8, wr_val)
#define rdc_eagle_tsc_cap_select_m_en()                         _eagle_tsc_pmd_rde_field_byte(0xd123, 8, 15, __ERR)
#define wrc_eagle_tsc_cap_select_m_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_cap_force_slowdown_en()                   _eagle_tsc_pmd_rde_field_byte(0xd123, 9, 15, __ERR)
#define wrc_eagle_tsc_cap_force_slowdown_en(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_cap_force_slowdown()                      _eagle_tsc_pmd_rde_field_byte(0xd123, 10, 15, __ERR)
#define wrc_eagle_tsc_cap_force_slowdown(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_cap_retry_en()                            _eagle_tsc_pmd_rde_field_byte(0xd123, 11, 15, __ERR)
#define wrc_eagle_tsc_cap_retry_en(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_cap_restart()                             _eagle_tsc_pmd_rde_field_byte(0xd123, 12, 15, __ERR)
#define wrc_eagle_tsc_cap_restart(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_cap_seq_cya()                             _eagle_tsc_pmd_rde_field_byte(0xd123, 13, 15, __ERR)
#define wrc_eagle_tsc_cap_seq_cya(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_cap_cnt_mask_en()                         _eagle_tsc_pmd_rde_field_byte(0xd123, 14, 15, __ERR)
#define wrc_eagle_tsc_cap_cnt_mask_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_fast_search_mode()                        _eagle_tsc_pmd_rde_field_byte(0xd123, 15, 15, __ERR)
#define wrc_eagle_tsc_fast_search_mode(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd123, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_lost_pll_lock_sm()                        _eagle_tsc_pmd_rde_field_byte(0xd128, 0, 15, __ERR)
#define rdc_eagle_tsc_cap_done()                                _eagle_tsc_pmd_rde_field_byte(0xd128, 1, 15, __ERR)
#define rdc_eagle_tsc_cap_pass()                                _eagle_tsc_pmd_rde_field_byte(0xd128, 2, 15, __ERR)
#define rdc_eagle_tsc_freq_done_sm()                            _eagle_tsc_pmd_rde_field_byte(0xd128, 3, 15, __ERR)
#define rdc_eagle_tsc_freq_pass_sm()                            _eagle_tsc_pmd_rde_field_byte(0xd128, 4, 15, __ERR)
#define rdc_eagle_tsc_pll_seq_done()                            _eagle_tsc_pmd_rde_field_byte(0xd128, 5, 15, __ERR)
#define rdc_eagle_tsc_pll_seq_pass()                            _eagle_tsc_pmd_rde_field_byte(0xd128, 6, 15, __ERR)
#define rdc_eagle_tsc_pll_lock()                                _eagle_tsc_pmd_rde_field_byte(0xd128, 7, 15, __ERR)
#define rdc_eagle_tsc_cap_done_lh_ll()                          _eagle_tsc_pmd_rde_field_byte(0xd128, 9, 15, __ERR)
#define rdc_eagle_tsc_cap_pass_lh_ll()                          _eagle_tsc_pmd_rde_field_byte(0xd128, 10, 15, __ERR)
#define rdc_eagle_tsc_freq_done_sm_lh_ll()                      _eagle_tsc_pmd_rde_field_byte(0xd128, 11, 15, __ERR)
#define rdc_eagle_tsc_freq_pass_sm_lh_ll()                      _eagle_tsc_pmd_rde_field_byte(0xd128, 12, 15, __ERR)
#define rdc_eagle_tsc_pll_seq_done_lh_ll()                      _eagle_tsc_pmd_rde_field_byte(0xd128, 13, 15, __ERR)
#define rdc_eagle_tsc_pll_seq_pass_lh_ll()                      _eagle_tsc_pmd_rde_field_byte(0xd128, 14, 15, __ERR)
#define rdc_eagle_tsc_pll_lock_lh_ll()                          _eagle_tsc_pmd_rde_field_byte(0xd128, 15, 15, __ERR)
#define rdc_eagle_tsc_res_cal_cntr()                            _eagle_tsc_pmd_rde_field_byte(0xd122, 0, 8, __ERR)
#define wrc_eagle_tsc_res_cal_cntr(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd122, 0xff00, 8, wr_val)
#define rdc_eagle_tsc_win_cal_cntr()                            _eagle_tsc_pmd_rde_field_byte(0xd122, 8, 8, __ERR)
#define wrc_eagle_tsc_win_cal_cntr(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd122, 0x00ff, 0, wr_val)
#define rdc_eagle_tsc_pre_freq_det_time()                       _eagle_tsc_pmd_rde_field_byte(0xd121, 0, 8, __ERR)
#define wrc_eagle_tsc_pre_freq_det_time(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd121, 0xff00, 8, wr_val)
#define rdc_eagle_tsc_retry_time()                              _eagle_tsc_pmd_rde_field_byte(0xd121, 8, 8, __ERR)
#define wrc_eagle_tsc_retry_time(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd121, 0x00ff, 0, wr_val)
#define rdc_eagle_tsc_vco_start_time()                          _eagle_tsc_pmd_rde_field_byte(0xd120, 0, 8, __ERR)
#define wrc_eagle_tsc_vco_start_time(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd120, 0xff00, 8, wr_val)
#define rdc_eagle_tsc_vco_step_time()                           _eagle_tsc_pmd_rde_field_byte(0xd120, 8, 8, __ERR)
#define wrc_eagle_tsc_vco_step_time(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd120, 0x00ff, 0, wr_val)
#define rd_eagle_tsc_signal_detect_filter_count()               _eagle_tsc_pmd_rde_field_byte(0xd0c0, 11, 11, __ERR)
#define wr_eagle_tsc_signal_detect_filter_count(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd0c0, 0x001f, 0, wr_val)
#define rd_eagle_tsc_los_filter_count()                         _eagle_tsc_pmd_rde_field_byte(0xd0c0, 3, 11, __ERR)
#define wr_eagle_tsc_los_filter_count(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0c0, 0x1f00, 8, wr_val)
#define rd_eagle_tsc_energy_detect_mask_count()                 _eagle_tsc_pmd_rde_field_byte(0xd0c1, 0, 11, __ERR)
#define wr_eagle_tsc_energy_detect_mask_count(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0xf800, 11, wr_val)
#define rd_eagle_tsc_afe_signal_detect_dis()                    _eagle_tsc_pmd_rde_field_byte(0xd0c1, 15, 15, __ERR)
#define wr_eagle_tsc_afe_signal_detect_dis(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0001, 0, wr_val)
#define rd_eagle_tsc_ext_los_en()                               _eagle_tsc_pmd_rde_field_byte(0xd0c1, 14, 15, __ERR)
#define wr_eagle_tsc_ext_los_en(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0002, 1, wr_val)
#define rd_eagle_tsc_ext_los_inv()                              _eagle_tsc_pmd_rde_field_byte(0xd0c1, 13, 15, __ERR)
#define wr_eagle_tsc_ext_los_inv(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0004, 2, wr_val)
#define rd_eagle_tsc_ignore_lp_mode()                           _eagle_tsc_pmd_rde_field_byte(0xd0c1, 12, 15, __ERR)
#define wr_eagle_tsc_ignore_lp_mode(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0008, 3, wr_val)
#define rd_eagle_tsc_signal_detect_filter_1us()                 _eagle_tsc_pmd_rde_field_byte(0xd0c1, 11, 15, __ERR)
#define wr_eagle_tsc_signal_detect_filter_1us(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0010, 4, wr_val)
#define rd_eagle_tsc_energy_detect_frc()                        _eagle_tsc_pmd_rde_field_byte(0xd0c1, 10, 15, __ERR)
#define wr_eagle_tsc_energy_detect_frc(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0020, 5, wr_val)
#define rd_eagle_tsc_energy_detect_frc_val()                    _eagle_tsc_pmd_rde_field_byte(0xd0c1, 9, 15, __ERR)
#define wr_eagle_tsc_energy_detect_frc_val(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0040, 6, wr_val)
#define rd_eagle_tsc_signal_detect_frc()                        _eagle_tsc_pmd_rde_field_byte(0xd0c1, 8, 15, __ERR)
#define wr_eagle_tsc_signal_detect_frc(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0080, 7, wr_val)
#define rd_eagle_tsc_signal_detect_frc_val()                    _eagle_tsc_pmd_rde_field_byte(0xd0c1, 7, 15, __ERR)
#define wr_eagle_tsc_signal_detect_frc_val(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0c1, 0x0100, 8, wr_val)
#define rd_eagle_tsc_los_thresh()                               _eagle_tsc_pmd_rde_field_byte(0xd0c2, 13, 13, __ERR)
#define wr_eagle_tsc_los_thresh(wr_val)                         _eagle_tsc_pmd_mwr_reg_byte(0xd0c2, 0x0007, 0, wr_val)
#define rd_eagle_tsc_signal_detect_thresh()                     _eagle_tsc_pmd_rde_field_byte(0xd0c2, 9, 13, __ERR)
#define wr_eagle_tsc_signal_detect_thresh(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0c2, 0x0070, 4, wr_val)
#define rd_eagle_tsc_hold_los_count()                           _eagle_tsc_pmd_rde_field_byte(0xd0c2, 5, 13, __ERR)
#define wr_eagle_tsc_hold_los_count(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd0c2, 0x0700, 8, wr_val)
#define rd_eagle_tsc_hold_sd_count()                            _eagle_tsc_pmd_rde_field_byte(0xd0c2, 2, 13, __ERR)
#define wr_eagle_tsc_hold_sd_count(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd0c2, 0x3800, 11, wr_val)
#define rd_eagle_tsc_signal_detect()                            _eagle_tsc_pmd_rde_field_byte(0xd0c8, 15, 15, __ERR)
#define rd_eagle_tsc_signal_detect_change()                     _eagle_tsc_pmd_rde_field_byte(0xd0c8, 14, 15, __ERR)
#define rd_eagle_tsc_energy_detect()                            _eagle_tsc_pmd_rde_field_byte(0xd0c8, 13, 15, __ERR)
#define rd_eagle_tsc_energy_detect_change()                     _eagle_tsc_pmd_rde_field_byte(0xd0c8, 12, 15, __ERR)
#define rd_eagle_tsc_signal_detect_raw()                        _eagle_tsc_pmd_rde_field_byte(0xd0c8, 11, 15, __ERR)
#define rd_eagle_tsc_signal_detect_raw_change()                 _eagle_tsc_pmd_rde_field_byte(0xd0c8, 10, 15, __ERR)
#define rd_eagle_tsc_afe_sigdet_thresh()                        _eagle_tsc_pmd_rde_field_byte(0xd0c8, 5, 13, __ERR)
#define rd_eagle_tsc_prbs_chk_clk_en_frc_on()                   _eagle_tsc_pmd_rde_field_byte(0xd0d1, 4, 15, __ERR)
#define wr_eagle_tsc_prbs_chk_clk_en_frc_on(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x0800, 11, wr_val)
#define rd_eagle_tsc_trnsum_error_count_en()                    _eagle_tsc_pmd_rde_field_byte(0xd0d1, 5, 15, __ERR)
#define wr_eagle_tsc_trnsum_error_count_en(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x0400, 10, wr_val)
#define rd_eagle_tsc_prbs_chk_err_cnt_burst_mode()              _eagle_tsc_pmd_rde_field_byte(0xd0d1, 6, 15, __ERR)
#define wr_eagle_tsc_prbs_chk_err_cnt_burst_mode(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x0200, 9, wr_val)
#define rd_eagle_tsc_prbs_chk_en_auto_mode()                    _eagle_tsc_pmd_rde_field_byte(0xd0d1, 8, 15, __ERR)
#define wr_eagle_tsc_prbs_chk_en_auto_mode(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x0080, 7, wr_val)
#define rd_eagle_tsc_prbs_chk_mode()                            _eagle_tsc_pmd_rde_field_byte(0xd0d1, 9, 14, __ERR)
#define wr_eagle_tsc_prbs_chk_mode(wr_val)                      _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x0060, 5, wr_val)
#define rd_eagle_tsc_prbs_chk_inv()                             _eagle_tsc_pmd_rde_field_byte(0xd0d1, 11, 15, __ERR)
#define wr_eagle_tsc_prbs_chk_inv(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x0010, 4, wr_val)
#define rd_eagle_tsc_prbs_chk_mode_sel()                        _eagle_tsc_pmd_rde_field_byte(0xd0d1, 12, 13, __ERR)
#define wr_eagle_tsc_prbs_chk_mode_sel(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x000e, 1, wr_val)
#define rd_eagle_tsc_prbs_chk_en()                              _eagle_tsc_pmd_rde_field_byte(0xd0d1, 15, 15, __ERR)
#define wr_eagle_tsc_prbs_chk_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0d1, 0x0001, 0, wr_val)
#define rd_eagle_tsc_prbs_chk_lock_cnt()                        _eagle_tsc_pmd_rde_field_byte(0xd0d0, 11, 11, __ERR)
#define wr_eagle_tsc_prbs_chk_lock_cnt(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0d0, 0x001f, 0, wr_val)
#define rd_eagle_tsc_prbs_chk_ool_cnt()                         _eagle_tsc_pmd_rde_field_byte(0xd0d0, 3, 11, __ERR)
#define wr_eagle_tsc_prbs_chk_ool_cnt(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0d0, 0x1f00, 8, wr_val)
#define rd_eagle_tsc_dig_lpbk_pd_flt_bypass()                   _eagle_tsc_pmd_rde_field_byte(0xd0d2, 13, 15, __ERR)
#define wr_eagle_tsc_dig_lpbk_pd_flt_bypass(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd0d2, 0x0004, 2, wr_val)
#define rd_eagle_tsc_dig_lpbk_pd_mode()                         _eagle_tsc_pmd_rde_field_byte(0xd0d2, 14, 15, __ERR)
#define wr_eagle_tsc_dig_lpbk_pd_mode(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0d2, 0x0002, 1, wr_val)
#define rd_eagle_tsc_dig_lpbk_en()                              _eagle_tsc_pmd_rde_field_byte(0xd0d2, 15, 15, __ERR)
#define wr_eagle_tsc_dig_lpbk_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0d2, 0x0001, 0, wr_val)
#define rd_eagle_tsc_dbg_mask_dig_lpbk_en()                     _eagle_tsc_pmd_rde_field_byte(0xd0d3, 13, 15, __ERR)
#define wr_eagle_tsc_dbg_mask_dig_lpbk_en(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd0d3, 0x0004, 2, wr_val)
#define rd_eagle_tsc_rx_aggregator_bypass_en()                  _eagle_tsc_pmd_rde_field_byte(0xd0d3, 14, 15, __ERR)
#define wr_eagle_tsc_rx_aggregator_bypass_en(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd0d3, 0x0002, 1, wr_val)
#define rd_eagle_tsc_rx_pmd_dp_invert()                         _eagle_tsc_pmd_rde_field_byte(0xd0d3, 15, 15, __ERR)
#define wr_eagle_tsc_rx_pmd_dp_invert(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0d3, 0x0001, 0, wr_val)
#define rd_eagle_tsc_prbs_chk_en_timeout()                      _eagle_tsc_pmd_rde_field_byte(0xd0d4, 3, 11, __ERR)
#define wr_eagle_tsc_prbs_chk_en_timeout(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd0d4, 0x1f00, 8, wr_val)
#define rd_eagle_tsc_prbs_chk_en_timer_mode()                   _eagle_tsc_pmd_rde_field_byte(0xd0d4, 14, 14, __ERR)
#define wr_eagle_tsc_prbs_chk_en_timer_mode(wr_val)             _eagle_tsc_pmd_mwr_reg_byte(0xd0d4, 0x0003, 0, wr_val)
#define rd_eagle_tsc_dig_lpbk_pd_early_ind()                    _eagle_tsc_pmd_rde_field_byte(0xd0d8, 14, 15, __ERR)
#define rd_eagle_tsc_dig_lpbk_pd_late_ind()                     _eagle_tsc_pmd_rde_field_byte(0xd0d8, 15, 15, __ERR)
#define rd_eagle_tsc_prbs_chk_lock()                            _eagle_tsc_pmd_rde_field_byte(0xd0d9, 15, 15, __ERR)
#define rd_eagle_tsc_prbs_chk_lock_lost_lh()                    _eagle_tsc_pmd_rde_field_byte(0xd0da, 0, 15, __ERR)
#define rd_eagle_tsc_prbs_chk_err_cnt_msb()                     _eagle_tsc_pmd_rde_field(0xd0da, 1, 1, __ERR)
#define rd_eagle_tsc_prbs_chk_err_cnt_lsb()                     _eagle_tsc_pmd_rde_reg(0xd0db, __ERR)
#define rd_eagle_tsc_pmd_rx_lock()                              _eagle_tsc_pmd_rde_field_byte(0xd0dc, 15, 15, __ERR)
#define rd_eagle_tsc_pmd_rx_lock_change()                       _eagle_tsc_pmd_rde_field_byte(0xd0dc, 14, 15, __ERR)
#define rd_eagle_tsc_patt_gen_start_pos()                       _eagle_tsc_pmd_rde_field_byte(0xd0e0, 0, 12, __ERR)
#define wr_eagle_tsc_patt_gen_start_pos(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0e0, 0xf000, 12, wr_val)
#define rd_eagle_tsc_patt_gen_stop_pos()                        _eagle_tsc_pmd_rde_field_byte(0xd0e0, 4, 12, __ERR)
#define wr_eagle_tsc_patt_gen_stop_pos(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0e0, 0x0f00, 8, wr_val)
#define rd_eagle_tsc_patt_gen_en()                              _eagle_tsc_pmd_rde_field_byte(0xd0e0, 15, 15, __ERR)
#define wr_eagle_tsc_patt_gen_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0e0, 0x0001, 0, wr_val)
#define rd_eagle_tsc_prbs_gen_err_ins()                         _eagle_tsc_pmd_rde_field_byte(0xd0e1, 10, 15, __ERR)
#define wr_eagle_tsc_prbs_gen_err_ins(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0e1, 0x0020, 5, wr_val)
#define rd_eagle_tsc_prbs_gen_inv()                             _eagle_tsc_pmd_rde_field_byte(0xd0e1, 11, 15, __ERR)
#define wr_eagle_tsc_prbs_gen_inv(wr_val)                       _eagle_tsc_pmd_mwr_reg_byte(0xd0e1, 0x0010, 4, wr_val)
#define rd_eagle_tsc_prbs_gen_mode_sel()                        _eagle_tsc_pmd_rde_field_byte(0xd0e1, 12, 13, __ERR)
#define wr_eagle_tsc_prbs_gen_mode_sel(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd0e1, 0x000e, 1, wr_val)
#define rd_eagle_tsc_prbs_gen_en()                              _eagle_tsc_pmd_rde_field_byte(0xd0e1, 15, 15, __ERR)
#define wr_eagle_tsc_prbs_gen_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0e1, 0x0001, 0, wr_val)
#define rd_eagle_tsc_rmt_lpbk_pd_frc_on()                       _eagle_tsc_pmd_rde_field_byte(0xd0e2, 13, 15, __ERR)
#define wr_eagle_tsc_rmt_lpbk_pd_frc_on(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd0e2, 0x0004, 2, wr_val)
#define rd_eagle_tsc_rmt_lpbk_pd_mode()                         _eagle_tsc_pmd_rde_field_byte(0xd0e2, 14, 15, __ERR)
#define wr_eagle_tsc_rmt_lpbk_pd_mode(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0e2, 0x0002, 1, wr_val)
#define rd_eagle_tsc_rmt_lpbk_en()                              _eagle_tsc_pmd_rde_field_byte(0xd0e2, 15, 15, __ERR)
#define wr_eagle_tsc_rmt_lpbk_en(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd0e2, 0x0001, 0, wr_val)
#define rd_eagle_tsc_tx_mux_sel_order()                         _eagle_tsc_pmd_rde_field_byte(0xd0e3, 13, 15, __ERR)
#define wr_eagle_tsc_tx_mux_sel_order(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0e3, 0x0004, 2, wr_val)
#define rd_eagle_tsc_tx_pcs_native_ana_frmt_en()                _eagle_tsc_pmd_rde_field_byte(0xd0e3, 14, 15, __ERR)
#define wr_eagle_tsc_tx_pcs_native_ana_frmt_en(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd0e3, 0x0002, 1, wr_val)
#define rd_eagle_tsc_tx_pmd_dp_invert()                         _eagle_tsc_pmd_rde_field_byte(0xd0e3, 15, 15, __ERR)
#define wr_eagle_tsc_tx_pmd_dp_invert(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd0e3, 0x0001, 0, wr_val)
#define rd_eagle_tsc_tx_pi_loop_timing_src_sel()                _eagle_tsc_pmd_rde_field_byte(0xd0e4, 15, 15, __ERR)
#define wr_eagle_tsc_tx_pi_loop_timing_src_sel(wr_val)          _eagle_tsc_pmd_mwr_reg_byte(0xd0e4, 0x0001, 0, wr_val)
#define rd_eagle_tsc_rmt_lpbk_pd_early_ind()                    _eagle_tsc_pmd_rde_field_byte(0xd0e8, 14, 15, __ERR)
#define rd_eagle_tsc_rmt_lpbk_pd_late_ind()                     _eagle_tsc_pmd_rde_field_byte(0xd0e8, 15, 15, __ERR)
#define rd_eagle_tsc_txfir_post_override()                      _eagle_tsc_pmd_rde_field_byte(0xd110, 5, 10, __ERR)
#define wr_eagle_tsc_txfir_post_override(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd110, 0x07e0, 5, wr_val)
#define rd_eagle_tsc_txfir_pre_override()                       _eagle_tsc_pmd_rde_field_byte(0xd110, 11, 11, __ERR)
#define wr_eagle_tsc_txfir_pre_override(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd110, 0x001f, 0, wr_val)
#define rd_eagle_tsc_txfir_override_en()                        _eagle_tsc_pmd_rde_field_byte(0xd111, 0, 15, __ERR)
#define wr_eagle_tsc_txfir_override_en(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd111, 0x8000, 15, wr_val)
#define rd_eagle_tsc_txfir_post2()                              _eagle_tsc_pmd_rde_field_signed_byte(0xd111, 4, 11, __ERR)
#define wr_eagle_tsc_txfir_post2(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd111, 0x0f80, 7, wr_val)
#define rd_eagle_tsc_txfir_main_override()                      _eagle_tsc_pmd_rde_field_byte(0xd111, 9, 9, __ERR)
#define wr_eagle_tsc_txfir_main_override(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd111, 0x007f, 0, wr_val)
#define rd_eagle_tsc_txfir_post2_offset()                       _eagle_tsc_pmd_rde_field_byte(0xd112, 0, 12, __ERR)
#define wr_eagle_tsc_txfir_post2_offset(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd112, 0xf000, 12, wr_val)
#define rd_eagle_tsc_txfir_post_offset()                        _eagle_tsc_pmd_rde_field_byte(0xd112, 4, 12, __ERR)
#define wr_eagle_tsc_txfir_post_offset(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd112, 0x0f00, 8, wr_val)
#define rd_eagle_tsc_txfir_main_offset()                        _eagle_tsc_pmd_rde_field_byte(0xd112, 8, 12, __ERR)
#define wr_eagle_tsc_txfir_main_offset(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd112, 0x00f0, 4, wr_val)
#define rd_eagle_tsc_txfir_pre_offset()                         _eagle_tsc_pmd_rde_field_byte(0xd112, 12, 12, __ERR)
#define wr_eagle_tsc_txfir_pre_offset(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd112, 0x000f, 0, wr_val)
#define rd_eagle_tsc_txfir_post_after_ovr()                     _eagle_tsc_pmd_rde_field_byte(0xd113, 5, 10, __ERR)
#define rd_eagle_tsc_txfir_pre_after_ovr()                      _eagle_tsc_pmd_rde_field_byte(0xd113, 11, 11, __ERR)
#define rd_eagle_tsc_txfir_main_after_ovr()                     _eagle_tsc_pmd_rde_field_byte(0xd114, 9, 9, __ERR)
#define rd_eagle_tsc_txfir_post_adjusted()                      _eagle_tsc_pmd_rde_field_byte(0xd115, 5, 10, __ERR)
#define rd_eagle_tsc_txfir_pre_adjusted()                       _eagle_tsc_pmd_rde_field_byte(0xd115, 11, 11, __ERR)
#define rd_eagle_tsc_txfir_post3_adjusted()                     _eagle_tsc_pmd_rde_field_signed_byte(0xd116, 0, 12, __ERR)
#define rd_eagle_tsc_txfir_post2_adjusted()                     _eagle_tsc_pmd_rde_field_signed_byte(0xd116, 4, 11, __ERR)
#define rd_eagle_tsc_txfir_main_adjusted()                      _eagle_tsc_pmd_rde_field_byte(0xd116, 9, 9, __ERR)
#define rd_eagle_tsc_micro_tx_disable()                         _eagle_tsc_pmd_rde_field_byte(0xd117, 15, 15, __ERR)
#define wr_eagle_tsc_micro_tx_disable(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd117, 0x0001, 0, wr_val)
#define rd_eagle_tsc_dp_reset_tx_disable_dis()                  _eagle_tsc_pmd_rde_field_byte(0xd118, 3, 15, __ERR)
#define wr_eagle_tsc_dp_reset_tx_disable_dis(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd118, 0x1000, 12, wr_val)
#define rd_eagle_tsc_tx_disable_output_sel()                    _eagle_tsc_pmd_rde_field_byte(0xd118, 4, 14, __ERR)
#define wr_eagle_tsc_tx_disable_output_sel(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd118, 0x0c00, 10, wr_val)
#define rd_eagle_tsc_tx_eee_alert_en()                          _eagle_tsc_pmd_rde_field_byte(0xd118, 6, 15, __ERR)
#define wr_eagle_tsc_tx_eee_alert_en(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd118, 0x0200, 9, wr_val)
#define rd_eagle_tsc_tx_eee_quiet_en()                          _eagle_tsc_pmd_rde_field_byte(0xd118, 7, 15, __ERR)
#define wr_eagle_tsc_tx_eee_quiet_en(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd118, 0x0100, 8, wr_val)
#define rd_eagle_tsc_tx_disable_timer_ctrl()                    _eagle_tsc_pmd_rde_field_byte(0xd118, 8, 10, __ERR)
#define wr_eagle_tsc_tx_disable_timer_ctrl(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd118, 0x00fc, 2, wr_val)
#define rd_eagle_tsc_pmd_tx_disable_pkill()                     _eagle_tsc_pmd_rde_field_byte(0xd118, 14, 15, __ERR)
#define wr_eagle_tsc_pmd_tx_disable_pkill(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd118, 0x0002, 1, wr_val)
#define rd_eagle_tsc_sdk_tx_disable()                           _eagle_tsc_pmd_rde_field_byte(0xd118, 15, 15, __ERR)
#define wr_eagle_tsc_sdk_tx_disable(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd118, 0x0001, 0, wr_val)
#define rd_eagle_tsc_txfir_post3_offset()                       _eagle_tsc_pmd_rde_field_byte(0xd119, 4, 12, __ERR)
#define wr_eagle_tsc_txfir_post3_offset(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd119, 0x0f00, 8, wr_val)
#define rd_eagle_tsc_txfir_post3()                              _eagle_tsc_pmd_rde_field_signed_byte(0xd119, 12, 12, __ERR)
#define wr_eagle_tsc_txfir_post3(wr_val)                        _eagle_tsc_pmd_mwr_reg_byte(0xd119, 0x000f, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_en()                                _eagle_tsc_pmd_rde_field_byte(0xd070, 15, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_en(wr_val)                          _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_jitter_filter_en()                  _eagle_tsc_pmd_rde_field_byte(0xd070, 14, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_jitter_filter_en(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_tx_pi_ext_ctrl_en()                       _eagle_tsc_pmd_rde_field_byte(0xd070, 13, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_ext_ctrl_en(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_tx_pi_freq_override_en()                  _eagle_tsc_pmd_rde_field_byte(0xd070, 12, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_freq_override_en(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_tx_pi_sj_gen_en()                         _eagle_tsc_pmd_rde_field_byte(0xd070, 11, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_sj_gen_en(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_tx_pi_ssc_gen_en()                        _eagle_tsc_pmd_rde_field_byte(0xd070, 10, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_ssc_gen_en(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_tx_pi_jit_ssc_freq_mode()                 _eagle_tsc_pmd_rde_field_byte(0xd070, 9, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_jit_ssc_freq_mode(wr_val)           _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0040, 6, wr_val)
#define rdc_eagle_tsc_tx_pi_second_order_loop_en()              _eagle_tsc_pmd_rde_field_byte(0xd070, 8, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_second_order_loop_en(wr_val)        _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0080, 7, wr_val)
#define rdc_eagle_tsc_tx_pi_first_order_bwsel_integ()           _eagle_tsc_pmd_rde_field_byte(0xd070, 6, 14, __ERR)
#define wrc_eagle_tsc_tx_pi_first_order_bwsel_integ(wr_val)     _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0300, 8, wr_val)
#define rdc_eagle_tsc_tx_pi_second_order_bwsel_integ()          _eagle_tsc_pmd_rde_field_byte(0xd070, 4, 14, __ERR)
#define wrc_eagle_tsc_tx_pi_second_order_bwsel_integ(wr_val)    _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x0c00, 10, wr_val)
#define rdc_eagle_tsc_tx_pi_ext_phase_bwsel_integ()             _eagle_tsc_pmd_rde_field_byte(0xd070, 1, 13, __ERR)
#define wrc_eagle_tsc_tx_pi_ext_phase_bwsel_integ(wr_val)       _eagle_tsc_pmd_mwr_reg_byte(0xd070, 0x7000, 12, wr_val)
#define rdc_eagle_tsc_tx_pi_freq_override_val()                 _eagle_tsc_pmd_rde_field_signed(0xd071, 1, 1, __ERR)
#define wrc_eagle_tsc_tx_pi_freq_override_val(wr_val)           eagle_tsc_pmd_mwr_reg(0xd071, 0x7fff, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_jit_freq_idx()                      _eagle_tsc_pmd_rde_field_byte(0xd072, 10, 10, __ERR)
#define wrc_eagle_tsc_tx_pi_jit_freq_idx(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd072, 0x003f, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_jit_amp()                           _eagle_tsc_pmd_rde_field_byte(0xd072, 2, 10, __ERR)
#define wrc_eagle_tsc_tx_pi_jit_amp(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd072, 0x3f00, 8, wr_val)
#define rdc_eagle_tsc_tx_pi_phase_override()                    _eagle_tsc_pmd_rde_field_byte(0xd073, 15, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_phase_override(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd073, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_phase_strobe()                      _eagle_tsc_pmd_rde_field_byte(0xd073, 14, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_phase_strobe(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd073, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_tx_pi_phase_step_dir()                    _eagle_tsc_pmd_rde_field_byte(0xd073, 13, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_phase_step_dir(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd073, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_tx_pi_phase_invert()                      _eagle_tsc_pmd_rde_field_byte(0xd073, 11, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_phase_invert(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd073, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_tx_pi_phase_step_num()                    _eagle_tsc_pmd_rde_field_byte(0xd073, 4, 12, __ERR)
#define wrc_eagle_tsc_tx_pi_phase_step_num(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd073, 0x0f00, 8, wr_val)
#define rdc_eagle_tsc_tx_pi_frz_frc()                           _eagle_tsc_pmd_rde_field_byte(0xd074, 15, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_frz_frc(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd074, 0x0001, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_frz_frc_val()                       _eagle_tsc_pmd_rde_field_byte(0xd074, 14, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_frz_frc_val(wr_val)                 _eagle_tsc_pmd_mwr_reg_byte(0xd074, 0x0002, 1, wr_val)
#define rdc_eagle_tsc_tx_pi_frz_mode()                          _eagle_tsc_pmd_rde_field_byte(0xd074, 13, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_frz_mode(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd074, 0x0004, 2, wr_val)
#define rdc_eagle_tsc_tx_pi_reset_code_dbg()                    _eagle_tsc_pmd_rde_field_byte(0xd074, 12, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_reset_code_dbg(wr_val)              _eagle_tsc_pmd_mwr_reg_byte(0xd074, 0x0008, 3, wr_val)
#define rdc_eagle_tsc_tx_pi_rmt_lpbk_bypass_flt()               _eagle_tsc_pmd_rde_field_byte(0xd074, 11, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_rmt_lpbk_bypass_flt(wr_val)         _eagle_tsc_pmd_mwr_reg_byte(0xd074, 0x0010, 4, wr_val)
#define rdc_eagle_tsc_tx_pi_frc_phase_step_mux_sel()            _eagle_tsc_pmd_rde_field_byte(0xd074, 10, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_frc_phase_step_mux_sel(wr_val)      _eagle_tsc_pmd_mwr_reg_byte(0xd074, 0x0020, 5, wr_val)
#define rdc_eagle_tsc_tx_pi_lane_sel_frc()                      _eagle_tsc_pmd_rde_field_byte(0xd076, 7, 15, __ERR)
#define wrc_eagle_tsc_tx_pi_lane_sel_frc(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd076, 0x0100, 8, wr_val)
#define rdc_eagle_tsc_tx_pi_lane_sel_frc_val()                  _eagle_tsc_pmd_rde_field_byte(0xd076, 11, 11, __ERR)
#define wrc_eagle_tsc_tx_pi_lane_sel_frc_val(wr_val)            _eagle_tsc_pmd_mwr_reg_byte(0xd076, 0x001f, 0, wr_val)
#define rdc_eagle_tsc_tx_pi_phase_cntr()                        _eagle_tsc_pmd_rde_field_signed_byte(0xd078, 9, 9, __ERR)
#define rdc_eagle_tsc_tx_pi_integ1_reg()                        _eagle_tsc_pmd_rde_field_signed(0xd079, 2, 2, __ERR)
#define rdc_eagle_tsc_tx_pi_integ2_reg()                        _eagle_tsc_pmd_rde_field_signed(0xd07a, 1, 1, __ERR)
#define rdc_eagle_tsc_tx_pi_phase_err()                         _eagle_tsc_pmd_rde_field_signed_byte(0xd07b, 10, 10, __ERR)
#define rdc_eagle_tsc_post_tap_limit()                          _eagle_tsc_pmd_rde_field_byte(0xd130, 5, 10, __ERR)
#define wrc_eagle_tsc_post_tap_limit(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd130, 0x07e0, 5, wr_val)
#define rdc_eagle_tsc_pre_tap_limit()                           _eagle_tsc_pmd_rde_field_byte(0xd130, 11, 11, __ERR)
#define wrc_eagle_tsc_pre_tap_limit(wr_val)                     _eagle_tsc_pmd_mwr_reg_byte(0xd130, 0x001f, 0, wr_val)
#define rdc_eagle_tsc_main_tap_limit()                          _eagle_tsc_pmd_rde_field_byte(0xd131, 9, 9, __ERR)
#define wrc_eagle_tsc_main_tap_limit(wr_val)                    _eagle_tsc_pmd_mwr_reg_byte(0xd131, 0x007f, 0, wr_val)
#define rdc_eagle_tsc_pre_tap_preset_val()                      _eagle_tsc_pmd_rde_field_byte(0xd132, 5, 11, __ERR)
#define wrc_eagle_tsc_pre_tap_preset_val(wr_val)                _eagle_tsc_pmd_mwr_reg_byte(0xd132, 0x07c0, 6, wr_val)
#define rdc_eagle_tsc_post_tap_preset_val()                     _eagle_tsc_pmd_rde_field_byte(0xd132, 10, 10, __ERR)
#define wrc_eagle_tsc_post_tap_preset_val(wr_val)               _eagle_tsc_pmd_mwr_reg_byte(0xd132, 0x003f, 0, wr_val)
#define rdc_eagle_tsc_tap_sum_max_val()                         _eagle_tsc_pmd_rde_field_byte(0xd133, 1, 8, __ERR)
#define wrc_eagle_tsc_tap_sum_max_val(wr_val)                   _eagle_tsc_pmd_mwr_reg_byte(0xd133, 0x7f80, 7, wr_val)
#define rdc_eagle_tsc_main_tap_min_val()                        _eagle_tsc_pmd_rde_field_byte(0xd133, 9, 9, __ERR)
#define wrc_eagle_tsc_main_tap_min_val(wr_val)                  _eagle_tsc_pmd_mwr_reg_byte(0xd133, 0x007f, 0, wr_val)
#define rdc_eagle_tsc_max_wait_timer_period()                   _eagle_tsc_pmd_rde_reg(0xd134, __ERR)
#define wrc_eagle_tsc_max_wait_timer_period(wr_val)             eagle_tsc_pmd_wr_reg(0xd134, wr_val)
#define rdc_eagle_tsc_wait_cntr_limit()                         _eagle_tsc_pmd_rde_field(0xd135, 7, 7, __ERR)
#define wrc_eagle_tsc_wait_cntr_limit(wr_val)                   eagle_tsc_pmd_mwr_reg(0xd135, 0x01ff, 0, wr_val)

#endif
